Abstract: Devices and methods of entraining a substance within an airflow are disclosed. Condensation aerosol delivery devices and methods of consistently producing multiple doses of a substance, such as a drug, having high purity, high yield, characterized by a particle size distribution appropriate for pulmonary delivery, and which can be administered to a user in a single dose are also disclosed.

Abstract: Devices and methods of entraining a substance within an airflow are disclosed. Condensation aerosol delivery devices and methods of consistently producing multiple doses of a substance, such as a drug, having high purity, high yield, characterized by a particle size distribution appropriate for pulmonary delivery, and which can be administered to a user in a single dose are also disclosed.

Abstract: Devices and methods of entraining a substance within an airflow are disclosed. Condensation aerosol delivery devices and methods of consistently producing multiple doses of a substance, such as a drug, having high purity, high yield, characterized by a particle size distribution appropriate for pulmonary delivery, and which can be administered to a user in a single dose are also disclosed.

Abstract: Devices and methods of entraining a substance within an airflow are disclosed. Condensation aerosol delivery devices and methods of consistently producing multiple doses of a substance, such as a drug, having high purity, high yield, characterized by a particle size distribution appropriate for pulmonary delivery, and which can be administered to a user in a single dose are also disclosed.

Abstract: Devices and methods of entraining a substance within an airflow are disclosed. Condensation aerosol delivery devices and methods of consistently producing multiple doses of a substance, such as a drug, having high purity, high yield, characterized by a particle size distribution appropriate for pulmonary delivery, and which can be administered to a user in a single dose are also disclosed.

Abstract: Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

Abstract: Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

Abstract: Apparatus for limiting the power consumption of a random access memory (RAM), comprising in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to said number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when said counter accumulates a count exceeding a predetermined value.

Abstract: The present invention relates to aerosols or thermal vapors formed from a drug inclusion complex that are used for inhalation therapy. In a method aspect of the invention, a method of delivering a drug to a mammal through an inhalation route is provided which comprises: heating a composition, wherein the composition comprises a drug inclusion complex, to form a drug aerosol or thermal vapor, which is inhaled by the mammal. In a kit aspect of the invention, a kit for delivering a drug through an inhalation route to a mammal is provided which comprises: a) a drug inclusion complex; and, b) a device that forms a drug aerosol or thermal vapor from the drug inclusion complex, for inhalation by the mammal.

Abstract: In a computer RAM memory system, the memory is subjected to a self test operation during which data is written to and read out from each address location of the memory. The data read out is compared with the written data to detect errors and the number of errors at each bit position is counted. When the number of errors in a bit position-exceeds a selected threshold, the corresponding DRAM is replaced by a spare DRAM. When the self test detects two or more errors in the same double word, the DRAM corresponding to the bit position having the highest error count is replaced with a spare DRAM. The memory is periodically scrubbed and errors detected during the scrubbing operation are counted for each bit position. At the end of the scrubbing of a chip row the DRAMs corresponding to bit positions at which the error counts exceed a selected threshold are replaced with spare DRAMs. When a multiple bit error in a double word is detected during scrubbing, the corresponding double word is tagged.

Abstract: Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

Abstract: In a memory card, identification numbers identifying the memory card are permanently stored in fuse blown registers formed in each of two redrive chips, which function to read out data from memory chips of the memory card and store data in the memory chips of the memory card. Each identification number separately provides a unique identification of the memory card. The identification numbers are each stored with an error correction code by which single bit errors en the identification numbers can be corrected and the occurrence of multiple bit errors in the identification numbers can be detected. Both identification numbers, if valid, are used to identify the memory card and both of the identification numbers, if valid, are stored in association with memory quality events occurring on the memory card, so as to provide a redundant identification of the memory card on which the memory quality events occurred.

Abstract: A barcode scanner, which is particularly suitable for reading barcode information from surfaces having various reflective properties, includes a light intensity control for the light source of the barcode scanner. The light intensity control preferably comprises a means for ramping voltage and a summing circuit which allows the current flowing through the light source to be controlled. In addition, the light intensity control utilizes a clocking means which controls the rate of voltage ramping.

Abstract: A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.

Abstract: A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory.

Abstract: A computer memory maintainence apparatus tests operating system storage and identifies a malfunctioning memory chip in an on-line memory array by detecting and recording all permanent data errors using data comparison along with data complementation and substitutes a spare memory chip for the malfunctioning one for all memory read commands. All write commands are performed on both spare memory and the malfunctioning memory chip. All contents of defective chip are copied to the spare chip. The computer system maintains the scrubbing and a recording counter for each of the data bits in an ECC memory data word. The sparing logic in the memory storage system maintains the bit steering logic and controls for the spare chip. When a counter is incremented above a threshold sparing is invoked to replace the failing bit position. The system writes to the defective and spare chips in parallel even after bit steering is invoked.