Patents by Inventor William Waller
William Waller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240409075Abstract: An assembly for a work vehicle includes an emergency portable hydraulic park brake release assembly for a spring applied, hydraulically released park brake. The portable hydraulic park brake release assembly includes a CO2 cartridge which is activated when the park brake is in the applied position. This causes gas from the CO2 cartridge to be introduced into a hydraulic conduit of the park brake to move to move the park brake to the released position. A method of operating same is also provided.Type: ApplicationFiled: June 12, 2023Publication date: December 12, 2024Inventor: William Waller Carson, IV
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Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration
Patent number: 12087350Abstract: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.Type: GrantFiled: September 25, 2020Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: William Waller, Cheng-Yi Huang -
MULTI-DECK NON-VOLATILE MEMORY ARCHITECTURE WITH IMPROVED WORDLINE BUS AND BITLINE BUS CONFIGURATION
Publication number: 20220101909Abstract: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: William Waller, Cheng-Yi Huang -
Patent number: 8892624Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. A method is provided to organize the distributed sites into a plurality of virtual organizations that can be further combined and virtualized into virtualized virtual organizations. These virtualized virtual organizations can also include additional distributed sites and existing virtualized virtual organizations and all members of a given virtualized virtual organization can share data and processing resources in order to process jobs on either a task-based or goal-based allocation mechanism. The virtualized virtual organization is created dynamically using ad-hoc collaborations among the members and is arranged in either a federated or cooperative architecture. Collaborations between members is either tightly-coupled or loosely coupled.Type: GrantFiled: May 11, 2007Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Michael J. Branson, Frederick Douglis, Bradley W. Fawcett, Zhen Liu, William Waller, Fan Ye
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Patent number: 8359347Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. The sites negotiate peering relationships to share data and processing resources to handle the submitted job requests. These peering relationships can be cooperative or federated and can be expressed using common interest policies. Each site within the system runs an instance of a system architecture for processing job requests and is therefore a self-contained, fully functional instance of the cooperative data stream processing system.Type: GrantFiled: April 10, 2007Date of Patent: January 22, 2013Assignee: International Business Machines CorporationInventors: Michael John Branson, Frederick Douglis, Bradley William Fawcett, Zhen Liu, William Waller, Fan Ye
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Patent number: 8119911Abstract: An electrical connection enclosure cover plate for use during drywall installation, texturing and painting processes, may include a single and unitary body having a rectangular and planar outer wall adapted to be affixed to an existing electrical box. The outer wall has a plurality of pins extending outwardly from an anterior face thereof. The pins are statically situated at opposed corners of the anterior face, and suitably sized and shaped to penetrate through an existing dry wall. The body has a plurality of primary panels directly connected to a posterior face of the outer wall. The primary panels may be adapted to frictionally engage the existing electrical box. The body may be adapted to be detachably coupled to the existing electrical box such that the outer wall may be adapted to cover and shield a front opening of the existing electrical box from undesirable debris and fluids.Type: GrantFiled: January 15, 2009Date of Patent: February 21, 2012Inventor: William Waller
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Publication number: 20080256253Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. The sites negotiate peering relationships to share data and processing resources to handle the submitted job requests. These peering relationships can be cooperative or federated and can be expressed using common interest policies. Each site within the system runs an instance of a system architecture for processing job requests and is therefore a self-contained, fully functional instance of the cooperative data stream processing system.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: International Business Machines CorporationInventors: Michael J. Branson, Frederick Douglis, Bradley W. Fawcett, Zhen Liu, William Waller, Fan Ye
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Publication number: 20080256548Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. A method is provided to organize the distributed sites into a plurality of virtual organizations that can be further combined and virtualized into virtualized virtual organizations. These virtualized virtual organizations can also include additional distributed sites and existing virtualized virtual organizations and all members of a given virtualized virtual organization can share data and processing resources in order to process jobs on either a task-based or goal-based allocation mechanism. The virtualized virtual organization is created dynamically using ad-hoc collaborations among the members and is arranged in either a federated or cooperative architecture. Collaborations between members is either tightly-coupled or loosely coupled.Type: ApplicationFiled: May 11, 2007Publication date: October 16, 2008Applicant: International Business Machines CorporationInventors: Michael J. Branson, Frederick Douglis, Bradley W. Fawcett, Zhen Liu, William Waller, Fan Ye
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Publication number: 20080216531Abstract: The invention relates to locking apparatus such as a door combination lock. The apparatus includes a lock housing having a number of code entry buttons mounted on its face. The buttons allow a user to enter a code combination in order to gain access through the door. In order to prevent deciphering of the code by an unauthorised user a load plate is provided to selectively impede actuation of the buttons between a released and a depressed configuration.Type: ApplicationFiled: February 25, 2008Publication date: September 11, 2008Applicant: Borg Locks LimitedInventors: Andrew William Waller, Joe Robert Charnley
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Publication number: 20080111574Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: January 21, 2008Publication date: May 15, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20080062793Abstract: A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or “re-store” the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array.Type: ApplicationFiled: November 5, 2007Publication date: March 13, 2008Inventors: William Waller, Eric Carman
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Publication number: 20070103167Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: May 10, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070075723Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: April 5, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070075722Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: April 5, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20070075725Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 1, 2006Publication date: April 5, 2007Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20060266950Abstract: An apparatus and method for measuring ozone in the atmosphere. The apparatus utilizes a fiber optic cable connected to a collimating lens located outdoors and a spectrometer that is located indoors. A pan-and-tilt positioning unit having a pan-axis capable of tracking an azimuth angle of the Sun, and a tilt-axis capable of tracking an elevation angle of the Sun, is utilized for automatically pointing the collimating lens directly at the Sun and taking readings for column ozone determination on any given day of the year. The apparatus and method utilizes a computer that is in electrical communication with the spectrometer and the pan-and-tilt unit.Type: ApplicationFiled: May 11, 2006Publication date: November 30, 2006Applicant: University of North TexasInventors: Miguel Acevedo, William Waller, Gilbert Nebgen
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Publication number: 20060192582Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: April 24, 2006Publication date: August 31, 2006Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20060126374Abstract: A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or “re-store” the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array.Type: ApplicationFiled: December 12, 2005Publication date: June 15, 2006Inventors: William Waller, Eric Carman
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Publication number: 20050093566Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: December 10, 2004Publication date: May 5, 2005Inventors: Warren Farnworth, William Waller, Leland Nevill, Raymond Beffa, Eugene Cloud
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Publication number: 20050018506Abstract: A dynamic random access memory sense amp equilibration and biasing circuit with reduced transistor count allowing an interstitial layout, thus substantially reducing circuit area requirements.Type: ApplicationFiled: July 23, 2003Publication date: January 27, 2005Inventor: William Waller