Abstract: Provided herein is a tool monitoring system and method of use. The tool monitoring system includes a plurality of panels forming a tunnel having a plurality of cameras disposed therein. The plurality of cameras take measurements of a tooling fixture, the tooling fixture having fixtures and features of interest thereon, as the tooling fixture moves in the tunnel. The system calculates a frame of reference of the tooling fixture and compares the actual position of one or more of the features of interest with the apparent position of the one or more features of interest in the frame of reference to determine an offset between the actual and apparent position of the of the one or more features of interest. The system then calculates a function to correct for the offset.

Abstract: A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

Abstract: In one aspect, the present invention overcomes the limitations of the prior art by provident a logic simulation ;system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.

Abstract: A processor system comprising a processor and a memory system with a high data transfer rate and low average power consumption of related I/O activity. The processor system may be disposed on a single circuit board. One embodiment of a disclosed system includes a processor system that comprises a processor device, a memory device and a circuit board. The circuit board includes a substrate, electrical contacts, and interconnection lines between the contacts. The electrical contacts of the circuit board may be coupled to electrical contacts on the processor device and the memory device. The interconnection lines communicate signals, such as data or instructions, between the electrical contacts of the memory device and the process device at least 200 billion bits per second while related input/output activity of the processor and the memory consumes an average power less than ten watts.

Abstract: In one aspect, logic simulation of a design of a semiconductor chip is performed on a domain-by-domain basis (e.g., by clock domain), but storing a history of the state space of the domain during simulation. In this way, additional information beyond just the end result can be reviewed in order to debug or otherwise analyze the design.

Abstract: A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation. In one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, predetermined offset to the user memory address. Thus, no address translation is required at run-time.

Abstract: A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

Abstract: A simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic operation, and a shift register for storing intermediate values generating during the logic simulation. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units can also include one or more bypass multiplexers coupled between the output of the processor element and the interconnect system, for providing a path for bypassing the shift register to provide the output of the processor element directly to the interconnect system.

Abstract: A method, apparatus, and system are provided for declining auction with interest rate bidding. According to one embodiment, an interest rate may be set for a transacted financial instrument, and information regarding the financial instrument and an interest rate at which the financial instrument is offered are published via a computer network. Offers from respective bidders to transact the financial instrument may be received, via the computer network, being expressed as offered interest rates at which the bidders are willing to transact the financial instrument. On the termination of a bid receiving process, whether at least one of the offers satisfies transaction criteria, as defined by a seller of the financial instrument, may be determined. If it is determined that at least one of the offers satisfies the transaction criteria, then at least one of the offers may be identified as an accepted offer.

Abstract: This invention provides electrophoresis gel container assemblies comprising at least a container element, a cover element, and means for releasably sealing the cover element to the container element; methods for fabricating and for using the container assemblies; and kits comprising the container assemblies with or without precast electrophoresis gels therein in combination with at least one electrophoresis auxiliary item.

Abstract: A suitable precursor for the production of carbon fibre is an acrylonitrile copolymer containing at least one non-acrylic moiety which is a carbonyl group a hydroxymethylene group, --CH(OH)-- or a two carbon moiety containing a carbonyl group or a hydroxymethylene group and in which the non-acrylonitrile moiety is present to the extent of 5 to 15 molar parts per 100 molar parts of acrylonitrile moiety.The preparation of such copolymers and their conversion to carbon fibre is described.

Abstract: A process for the production of carbon fibres is described in which a precursor fibre which is a copolymer of acrylonitrile, a chlorinated monomer, and itaconic acid containing between 2 to 20 molar parts of chlorinated comoner, between 0.5 and 5 molar parts of itaconic acid and 0 to 5 molar parts of other comonomers per 100 molar parts of acrylonitrile to a temperature in the range 200.degree.-400.degree. C while the natural shrinkage of the fibre is at least restrained followed by further heat treatment at a temperature in the range 800.degree.-3000.degree. C in a non-oxidizing atmosphere.

Abstract: A process for the production of a carbon article is provided by which a synthetic organic fibre which is capable of conversion to high strength, high modulus carbon fibre and which has been partially so converted is impregnated with a synthetic organic resin and the resin/fibre impregnate subject to a carbonization treatment in an inert atmosphere at a temperature of at least 1000.degree. C. Preferably the fibre is polyacrylonitrile which has been heated at a temperature of 200.degree. to 250.degree. C in an oxidizing atmosphere. The resin may be a phenol/formaldehyde resin, a polyvinylidene chloride resin or a polyfurfuryl alcohol resin. The process is particularly suited to the production of carbon articles in the form of fibre or rod by drawing the fibre first through the resin to impregnate it and then through a die to form the resin/fibre impregnate.