Abstract: For multiple layer interconnections using copper, the top interconnection layer and the via hole to the bottom layer are self-aligned on at least one side. The self-alignment eliminates the need for providing a border for the contact of the via hole to the interconnection. The self-alignment is accomplished by using a nitride mask, which defines one side of both the via hole and the interconnection. After the top surface of the copper interconnection is planarized, another layer of copper interconnection can be superimposed over the first interconnection in a similar manner.

Abstract: A semiconductor wafer is planarized by first mapping the flatness profile and then etching the wafer according to the flatness profile. Mapping is accomplished by scanning the wafer with a light beam. The flatness information is obtained by a phase detector comparing the phase of the reflected light beam and a reference light, and is then stored in a memory. The etching is implemented with scanning chemical ion beam etching, in which a reactive gas etches the wafer from spot to spot according to the instantaneous volume of reacting gas or the potential at the wafer, and is controlled by the data stored in the memory. The method can be used to planarize both semiconductor and metal.