Patents by Inventor William Wille

William Wille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150279243
    Abstract: A paint identification label apparatus having a rectangular shaped structure with a first side and a second side, wherein the second side thereof provides an adhesive having a peel back cover or film thereover. The first side provides a material that is adapted to be written upon via a writing implement, wherein the user can dispose the name of a paint color thereon for indication to users of the paint color in a specific room. The device can have several embodiments, wherein one embodiment can be placed over a light switch and another embodiment can be placed over a wall outlet plug. Thereafter, the user can place a light switch cover or wall outlet plate over the paint identification label for concealment until removed by the user.
    Type: Application
    Filed: February 18, 2015
    Publication date: October 1, 2015
    Inventor: William Willes
  • Patent number: 7705314
    Abstract: A method for reducing a need for physical memory includes compressing a sub-region of an intermediate histogram to obtain a compressed result, and storing the compressed result in a physical or virtual file.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 27, 2010
    Assignee: General Electric Company
    Inventors: Michael Joseph Cook, Mark William Wille
  • Publication number: 20070278409
    Abstract: A method for reducing a need for physical memory includes compressing a sub-region of an intermediate histogram to obtain a compressed result, and storing the compressed result in a physical or virtual file.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventors: Michael Joseph Cook, Mark William Wille
  • Publication number: 20070122965
    Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 31, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, William Henson, Kern Rim, William Wille
  • Publication number: 20070069294
    Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, William Henson, Kern Rim, William Wille
  • Publication number: 20050023581
    Abstract: A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 3, 2005
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: Joachim Nuetzel, Xian Jay Ning, William Wille
  • Patent number: 6361402
    Abstract: A method for polishing an object having a layer of photoresist, the method, employing the following steps: a) applying a layer of slurry on an a layer of photoresist on an object having a first and a second side, the layer of photoresist on one of the first and second side, the object having a center axis perpendicular to the first and second side; b) contacting the layer of slurry with a pad having a first and second side, the first side of the pad exerting a force on the slurry.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: March 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Canaperi, Rangarajan Jagannathan, Mahadevaiyer Krishnan, Max G. Levy, Uma Satyendra, Matthew Sendelbach, James A. Tornello, William Wille