Abstract: A battery comprising a lithium metal anode; a solid electrolyte; a cathode; and at least one interface layer between a surface of the cathode and a surface of the solid electrolyte, the interface layer formed of a printable lithium composition comprised of lithium metal powder, a polymer binder compatible with the lithium metal powder, a rheology modifier compatible with the lithium metal powder, and a solvent compatible with the lithium metal powder and with the polymer binder, wherein the interface layer improves the uniformity of the surface of the solid electrolyte thereby optimizing contact between the surface of the cathode and the surface of the solid electrolyte for better battery performance.

Abstract: A system and a method include a control unit for determining a probable de-icing status for one or more aircraft scheduled to depart from one or more airports. The control unit is configured to determine the probable de-icing status based on a current date at the one or more airports, current weather at the one or more airports, and the actual de-icing status of a plurality of prior aircraft scheduled to depart from the one or more airports before the one or more aircraft.

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

Abstract: Temperature sensors using bipolar junction transistors are provided. Examples of the disclosed sensors minimize effects of IR drop and have improved accuracy. An example temperature sensor includes a first branch coupled between a power supply and ground. The first branch includes a first transistor series-coupled with a second transistor via a first node and has a first temperature sensor output via the first node. The temperature sensor also includes a second branch coupled between the power supply and ground. The second branch includes a third transistor series-coupled with a fourth transistor via a second node and has a second temperature sensor output via the second node. The first through fourth transistors are diode-connected and can have an n-well structure or a deep n-well structure. The temperature sensor also includes a voltage sensor having an input coupled to the first temperature sensor output and the second temperature sensor output.

Abstract: An apparatus includes a first component layer. The component layer includes a first semiconductor device. The apparatus further includes a first hydrophilic layer and a first hydrophobic layer. The first hydrophobic layer is positioned between the first component layer and the first hydrophilic layer. The apparatus further includes a first contact extending through the first hydrophobic layer and the first hydrophilic layer.

Abstract: Temperature sensors using bipolar junction transistors are provided. Examples of the disclosed sensors minimize effects of IR drop and have improved accuracy. An example temperature sensor includes a first branch coupled between a power supply and ground. The first branch includes a first transistor series-coupled with a second transistor via a first node and has a first temperature sensor output via the first node. The temperature sensor also includes a second branch coupled between the power supply and ground. The second branch includes a third transistor series-coupled with a fourth transistor via a second node and has a second temperature sensor output via the second node. The first through fourth transistors are diode-connected and can have an n-well structure or a deep n-well structure. The temperature sensor also includes a voltage sensor having an input coupled to the first temperature sensor output and the second temperature sensor output.

Abstract: A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the storage element is equal to or greater than a predetermined minimum spacing requirement. A width of the bottom electrode (BE) plate is substantially equal to a width of an active layer or a width of a plurality of metal layers.

Abstract: A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the storage element is equal to or greater than a predetermined minimum spacing requirement. A width of the bottom electrode (BE) plate is substantially equal to a width of an active layer or a width of a plurality of metal layers.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line.

Abstract: A low loading pad for a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The low loading pad includes a plurality of hollow-shaped lower metal layers and a top metal layer formed on an uppermost layer of the plurality of hollow-shaped lower metal layers.

Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.

Abstract: Electronic devices, such as IC devices, are tested by determining a failure net within the electronic device that is causing a device failure. After identifying the failure net, the failure net is locally stressed. The stress is applied so that only the net being tested is subjected to the stress, and the remaining nets and components of the device are not stressed. A change in a signal produced by the failure net is observed while the failure net is being subjected to the stress. Testing in this manner assists in identifying the failure net as a failure source of the device.

Abstract: Electronic devices, such as IC devices, are tested by determining a failure net within the electronic device that is causing a device failure. After identifying the failure net, the failure net is locally stressed. The stress is applied so that only the net being tested is subjected to the stress, and the remaining nets and components of the device are not stressed. A change in a signal produced by the failure net is observed while the failure net is being subjected to the stress. Testing in this manner assists in identifying the failure net as a failure source of the device.