Abstract: Methods and apparatuses for a self-supervised AI for reconstructing generalized CSI feedback in a wireless communication system. The method of a BS comprises: recovering at least one RB-level precoder based on at least one low-resolution RB-level precoder for obtaining a precoder gain; configuring, based on the at least one RB-level precoder, an up-sampling operation for CSI to train a self-supervised learning model without information including at least one of UL CSI or a reference signal; reconstructing, based on a physics-based loss function, the CSI using the self-supervised learning model for DL CSI; and transmitting, to a UE, signals including information associated with the reconstructed CSI.

Abstract: Apparatuses and methods for operating a base station (BS) are provided. In one embodiment, a method for operating a BS is provided. The method includes determining at least one correlation between an uplink (UL) channel state information (CSI) data and downlink (DL) CSI data using a deep learning-based CSI up-sampling model, and determining resource block-level (RB-level) DL CSI information using the deep learning-based CSI up-sampling model based on the correlation between the UL CSI data and the DL CSI data.

Abstract: A method includes: receiving, by a first electronic device located in a first site, a signal from a second electronic device over a channel; obtaining, by the first electronic device, a noisy channel estimate based on the received signal using a linear estimator; preprocessing, by the first electronic device, the noisy channel estimate to remove at least one of an anomaly, a multiuser interference, or a timing offset; and estimating, by the first electronic device, the channel using an artificial intelligence channel estimation model.

Abstract: Apparatuses and methods include: receiving, by a first electronic device, a signal from a second electronic device on a channel, the received signal modified by a noise, the channel associated with a channel matrix for multiple antennas; buffering antenna data from the multiple antennas; obtaining a noisy channel based on the buffered antenna data and a least squares estimate of the channel matrix; preprocessing the noisy channel jointly across the multiple antennas; inputting the preprocessed noisy channel to a channel estimation model trained to denoise the preprocessed noisy channel; and estimating the channel matrix based on denoising of the preprocessed noisy channel.

Abstract: A method of channel estimation includes: receiving, at a first electronic device, a signal from a second electronic device on a channel, the received signal modified by a noise, the channel associated with a channel matrix; obtaining a noisy channel based on the received signal and a least squares estimate of the channel matrix; preprocessing the noisy channel to remove at least one of a timing offset, a multiuser interference, or an intercell interference; inputting the preprocessed noisy channel to a CE model trained to perform CE based on the preprocessed noisy channel, the CE model comprising residual learning networks; and estimating the channel matrix based on denoising of the preprocessed noisy channel.

Abstract: A method for channel estimation includes: receiving, by a first electronic device, a signal indicative of a state of a channel from a second electronic device, the signal being associated with a channel matrix and corrupted by a noise; obtaining a noisy image of the channel in a first domain, the noisy image being a least squares estimate of the channel matrix; transforming the noisy image into a second domain; and performing channel estimation (CE) of the channel based on (i) the transformed noisy image, (ii) a CE model configured to denoise an input signal, and (iii) a sparsity of channel state information (CSI) in the transformed noisy image in the second domain.

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

Abstract: Temperature sensors using bipolar junction transistors are provided. Examples of the disclosed sensors minimize effects of IR drop and have improved accuracy. An example temperature sensor includes a first branch coupled between a power supply and ground. The first branch includes a first transistor series-coupled with a second transistor via a first node and has a first temperature sensor output via the first node. The temperature sensor also includes a second branch coupled between the power supply and ground. The second branch includes a third transistor series-coupled with a fourth transistor via a second node and has a second temperature sensor output via the second node. The first through fourth transistors are diode-connected and can have an n-well structure or a deep n-well structure. The temperature sensor also includes a voltage sensor having an input coupled to the first temperature sensor output and the second temperature sensor output.

Abstract: An apparatus includes a first component layer. The component layer includes a first semiconductor device. The apparatus further includes a first hydrophilic layer and a first hydrophobic layer. The first hydrophobic layer is positioned between the first component layer and the first hydrophilic layer. The apparatus further includes a first contact extending through the first hydrophobic layer and the first hydrophilic layer.

Abstract: Temperature sensors using bipolar junction transistors are provided. Examples of the disclosed sensors minimize effects of IR drop and have improved accuracy. An example temperature sensor includes a first branch coupled between a power supply and ground. The first branch includes a first transistor series-coupled with a second transistor via a first node and has a first temperature sensor output via the first node. The temperature sensor also includes a second branch coupled between the power supply and ground. The second branch includes a third transistor series-coupled with a fourth transistor via a second node and has a second temperature sensor output via the second node. The first through fourth transistors are diode-connected and can have an n-well structure or a deep n-well structure. The temperature sensor also includes a voltage sensor having an input coupled to the first temperature sensor output and the second temperature sensor output.

Abstract: A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the storage element is equal to or greater than a predetermined minimum spacing requirement. A width of the bottom electrode (BE) plate is substantially equal to a width of an active layer or a width of a plurality of metal layers.

Abstract: A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the storage element is equal to or greater than a predetermined minimum spacing requirement. A width of the bottom electrode (BE) plate is substantially equal to a width of an active layer or a width of a plurality of metal layers.

Abstract: A low loading pad for a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The low loading pad includes a plurality of hollow-shaped lower metal layers and a top metal layer formed on an uppermost layer of the plurality of hollow-shaped lower metal layers.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line.

Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.