Abstract: An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface.

Abstract: The present invention is an improvement in a molded semiconductor package and the method for its manufacture. The package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, a lid on the molding compound, and a heat pipe extending between the semiconductor die and the lid. Preferably, the heat pipe is formed so that it encircles the die. The package is assembled by mounting the die on the substrate, applying the molding compound to the substrate while a channel is formed in the molding compound adjacent the semiconductor die, inserting a heat pipe material in the channel, and mounting the lid on the molding compound and the heat pipe material.

Abstract: A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.

Abstract: A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.

Abstract: A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.

Abstract: Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test structures in scribelines that abut edges of the die. A reticle can be used to form additional test structures that are separated from the primary die. A gap is formed between the additional test structures and the primary die in each exposure. In subsequent exposures, test structures for adjacent die are formed in the gaps between the previously formed primary die and their additional test structures. These techniques are used to provide larger test structure area between each primary die. A blade can be used to block portions of the reticle that form the additional test structures. The reticle can then be used to pattern die with smaller test structures during high volume chip production.

Abstract: An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface.

Abstract: A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.

Abstract: Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test structures in scribelines that abut edges of the die. A reticle can be used to form additional test structures that are separated from the primary die. A gap is formed between the additional test structures and the primary die in each exposure. In subsequent exposures, test structures for adjacent die are formed in the gaps between the previously formed primary die and their additional test structures. These techniques are used to provide larger test structure area between each primary die. A blade can be used to block portions of the reticle that form the additional test structures. The reticle can then be used to pattern die with smaller test structures during high volume chip production.

Abstract: A method for analyzing a structured integrated circuit is provided. The method includes identifying a random logic region of the structured integrated circuit. The structured integrated circuit includes a predefined layout for transistors and basic interconnections to define a set of logic elements. A tile array of basic logic cells is integrated throughout the identified random logic region. The tile array of basic logic cells is defined from the set of logic elements of the structured integrated circuit. The tile array of basic cells enables communication of testing signals along the tile array of basic logic cells in a first and a second direction. The first and second directions are different from one another. The testing signals help to identify one or more errors in the tile array of basic logic cells. The array format assists in diagnosing and curing defects in the tile array of basic logic cells. The errors are pinpointed to a basic logic cell at the intersection of the first and second direction.

Abstract: The present invention is a novel method and apparatus for burn-in testing an electronic device. A device under test (DUT) is attached to a burn-in board (BIB), a thermally conductive sheet is placed atop the DUT, the BIB is placed in an environmentally-controlled burn-in oven, and current is applied to the DUT. A test signal can be sent to the DUT and data received from the DUT to determine whether the DUT is working properly. Aluminum, copper, or any material as thermally conductive as aluminum may be used in the sheet. The sheet may have top or bottom surface areas that conduct more heat away from the device and into the ambient environment than that conducted by a flat sheet. The sheet may be applied to a plurality of DUTs simultaneously. Further, a second thermally conductive sheet may be located underneath the BIB and in thermal contact with it.

Abstract: Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test structures in scribelines that abut edges of the die. A reticle can be used to form additional test structures that are separated from the primary die. A gap is formed between the additional test structures and the primary die in each exposure. In subsequent exposures, test structures for adjacent die are formed in the gaps between the previously formed primary die and their additional test structures. These techniques are used to provide larger test structure area between each primary die. A blade can be used to block portions of the reticle that form the additional test structures. The reticle can then be used to pattern die with smaller test structures during high volume chip production.

Abstract: An electronic package is disclosed with an underfill with multiple areas of different stiffness and a method of constructing same. An underfill shell region that contacts the chip and the substrate is stiffer than an underfill build region that does not contact either the chip or the substrate. The variation in stiffness may be achieved using materials in the shell that include more filler and/or less solvents than the materials in the bulk region. The underfill may also be composed of a single material with an adhesion to the chip and substrate that is stronger than the material's internal cohesion (e.g., a long chain polymer with an active carboxyl group at the end of the chain). This can be achieved by exposing the chip and substrate surfaces to a curing substance (e.g., vaporized hydrofluoric acid).

Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.

Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.

Abstract: A method is provided for making conductive structures whereby an insulating layer is formed over a substrate. A conductive layer is then formed over the insulating layer. A first photoresist layer is formed over the conductive layer, patterned and developed. The conductive layer is etched after which the first photoresist layer is removed. A second photoresist layer is formed over the integrated circuit, patterned and developed. The remaining regions of the conductive layer forming an interconnect or a gate are partially etched to form two-tiered stepped sidewalls.