Patents by Inventor William Yeh
William Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240141049Abstract: The present invention provides Wnt pathway agonists and related compositions, which may be used in any of a variety of therapeutic methods for the treatment of diseases.Type: ApplicationFiled: July 28, 2023Publication date: May 2, 2024Inventors: Yang LI, Tom Zhiye YUAN, Aaron Ken SATO, Wen-Chen YEH, Claudia Yvonne JANDA, Tristan William FOWLER, Helene BARIBAULT, Kuo-Pao LAI, Liqin XIE, Randall J. BREZSKI, Chenggang LU
-
Patent number: 11947949Abstract: A method that includes receiving a request to generate a data package for deployment in a target database environment. The request may indicate a first set of data objects from a first configuration associated with a source database environment. The method may further include determining a second set of data objects that are related to the first set of data objects based on the request and on a mapping between the first set of data objects and the second set of data objects. The method may further include transmitting an indication of the second set of data objects to a user at a user interface. The method may further include receiving a selection of one or more data objects from the second set of data objects for inclusion in the data package. The method may further include generating the data package based on the selection.Type: GrantFiled: January 25, 2022Date of Patent: April 2, 2024Assignee: Salesforce, Inc.Inventors: Sahil Bhutani, William Yeh, Naveen Singh Jaunk
-
Publication number: 20230236816Abstract: A method that includes receiving a request to generate a data package for deployment in a target database environment. The request may indicate a first set of data objects from a first configuration associated with a source database environment. The method may further include determining a second set of data objects that are related to the first set of data objects based on the request and on a mapping between the first set of data objects and the second set of data objects. The method may further include transmitting an indication of the second set of data objects to a user at a user interface. The method may further include receiving a selection of one or more data objects from the second set of data objects for inclusion in the data package. The method may further include generating the data package based on the selection.Type: ApplicationFiled: January 25, 2022Publication date: July 27, 2023Inventors: Sahil Bhutani, William Yeh, Naveen Singh Jaunk
-
Patent number: 11323532Abstract: Methods, systems, and devices for data packaging at an application server are described. According to the techniques described herein, a device (e.g., an application server) may receive a link to a data stream package that defines metadata of a data source and an import schedule associated with importing streaming data from the data source to a data target associated with the application server. The device may install the data stream package based on the received link and import the streaming data from the data source according to the import schedule based on installing the data stream package. The device may then map, based on the metadata of the data source defined in the data stream package, a set of source data fields of the data source to a set of target data fields of the data target.Type: GrantFiled: January 29, 2021Date of Patent: May 3, 2022Assignee: salesforce.com, inc.Inventors: Sahil Bhutani, Naveen Singh Jaunk, William Yeh
-
Patent number: 7746139Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and includes a number of radiation hardened D-type flip flops. The radiation hardened D-type flip flop circuits are designed to keep running properly at GHz frequencies in the presence of single event upset (SEU) hits. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs and each consists of a master latch and a slave latch connected in tandem. The master and slave latches each consist of two latch half circuits having dual complementary inputs and outputs that are mutually interconnected in a dual interlocked cell (DICE) configuration, with the result that the D-type flip flop is immune to an SEU affecting at most one of the flip flop's four dual complementary data inputs.Type: GrantFiled: March 27, 2008Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventor: William Yeh-Yung Mo
-
Radiation hardened phase frequency detector for implementing enhanced radiation immunity performance
Patent number: 7683675Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.Type: GrantFiled: August 8, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventor: William Yeh-Yung Mo -
Radiation hardened phase frequency detector for implementing enhanced radiation immunity performance
Patent number: 7482842Abstract: A radiation hardened phase frequency detector (PFD) is provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.Type: GrantFiled: September 15, 2006Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventor: William Yeh-Yung Mo -
Patent number: 7474134Abstract: The present invention provides a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.Type: GrantFiled: October 25, 2007Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventor: William Yeh-Yung Mo
-
Publication number: 20080290903Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.Type: ApplicationFiled: August 8, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: William Yeh-Yung Mo
-
Publication number: 20080235638Abstract: A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventor: William Yeh-Yung MO
-
Publication number: 20080211558Abstract: A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.Type: ApplicationFiled: March 27, 2008Publication date: September 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: William Yeh-Yung Mo
-
Patent number: 7362154Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.Type: GrantFiled: May 18, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventor: William Yeh-Yung Mo
-
Publication number: 20080068044Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Inventor: William Yeh-Yung Mo
-
Publication number: 20080072200Abstract: A method and radiation hardened phase frequency detector (PFD) for implementing enhanced radiation immunity performance, and a design structure on which the subject PFD circuit resides are provided. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.Type: ApplicationFiled: October 9, 2007Publication date: March 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: William Yeh-Yung Mo
-
Publication number: 20070268055Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Inventor: William Yeh-Yung Mo
-
Patent number: D637236Type: GrantFiled: December 29, 2009Date of Patent: May 3, 2011Inventors: Myk Lum, Yu Chuan Chang, William Yeh
-
Patent number: D841400Type: GrantFiled: September 15, 2016Date of Patent: February 26, 2019Assignee: 80 Percent Arms Inc.Inventors: Myk Lum, William Yeh, Kasin Chan
-
Patent number: D879558Type: GrantFiled: February 4, 2019Date of Patent: March 31, 2020Assignee: 80 Percent Arms Inc.Inventors: Myk Lum, William Yeh, Kasin Chan