Abstract: Impulse noise suppression upstream of digital processing circuitry contains a sample and hold mechanism which samples the input signal and stores a plurality of sequential sample values respectively representative of the amplitude of the input signal at successive sample times. The contents of the sample and hold mechanism are compared with an input signal sample to determine whether or not the there are abnormal amplitude variations which potentially constitute impulse noise. In one embodiment the comparison is referenced to the average magnitude of the input signal. In another embodiment the input signal is coupled to a cascaded arrangement of sample and hold circuits which sample and store a plurality of sequential sample values. The time differentials between successive sampling times are such there is little likelihood of occurrences of impulse noise spikes during any two successive sample intervals.

Abstract: A linear force actuator system for stabilizing a support structure employs a linear dc motor whose primary winding is driven by a pulse width modulation control signal representative of a force input, through which the secondary member of the motor which acts as an inertial mass, is to be controllably translated. For improved control accuracy, the actuator system of the invention employs a pair of feedback loops, one of which monitors the current in the motor's primary winding to maintain a constant force output to the secondary member and a secondary of which monitors long term deviations from the center of the secondary member and corrects for centering offsets. An opto-electronic position sensing arrangement monitors the movement of the secondary member whereby precise control of commutation of the coils of the primary winding and a smooth translation of the secondary member are obtained.

Abstract: A repeatered, multichannel fiber optic communication network includes a plurality of full duplex fiber optic channels and one or more auxiliary channels. In order to supervise and control the operation of the network, for both data transmission and fault/maintenance actions, each terminal station contains a processor-based subsystem capable of network monitoring, first level maintenance action, fault isolation, and remote network control and status reporting. This processor-based subsystem interfaces with each fiber optic channel, with an orderwire communication link, and with external input/output devices and surveillance equipment. Three substantially autonomous processor-based sections which are dedicated to performing specific functions within the overall network operation are employed for carrying out these separate interfacing tasks.

Abstract: A bit synchronizer for T-4 fiber optic data communication environments is configured of an input buffer amplifier to which the data to be regenerated is applied. The input buffer provides isolation between upstream signal processing circuitry and a bit rate generator coupled to the output of the buffer. Also coupled to the buffer output is a bit decision circuit essentially configured of a limiter and output flip-flop. The bit rate generator employs a limiter and dual delay logic circuitry connected in series that provide a strong bit rate component which is phase coherent with the input NRZ data transitions. Unwanted baseband components are removed by a bandpass filter the output of which, as the output of the bit rate generator, is coupled to a phase locked loop from which a crystal oscillator clock synchronized with the data transitions is produced to clock the output flip-flop in the bit decision circuit.