Abstract: An electrostatic discharge (ESD) protection circuit for use in an integrated circuit includes a transistor, an inverter, and an ESD detector. The transistor is coupled to clamp a non-power supply pad of the integrated circuit to a power supply pad of the integrated circuit when an ESD event is detected. The ESD detector is operably coupled to detect an ESD event on the non-power supply pad and to provide an indication of the ESD event to the inverter. The inverter provides an amplified signal to the gate of the transistor such that the transistor is driven quickly into low impedance conduction.

Abstract: An improved switch capacitor circuit includes a capacitor, a 1st voltage reference module, a 2nd voltage reference module, and a plurality of switching elements. The capacitor is operably coupled via the plurality of switching elements to sample an input signal during a 1st interval of a sampling period and during a 2nd interval of the sampling period to provide a representation of the input signal. The 2nd reference module produces a 2nd reference voltage that is representative of the common mode of the supply (e.g. VDD and VSS). The 1st voltage reference module produces a 1st reference voltage that is representative of the common mode of the analog input signal. As such, the capacitor is charged during the 1st interval based on the 1st reference voltage and discharged during the 2nd interval based on the 2nd reference voltage.