Abstract: The invention relates to a method for the manufacture of insulating portions separating the active regions of a VLSI CMOS circuit wherein an oxide coated silicon substrate is etched in those regions in which minimal insulation is to be required by etching trenches in the oxide insulating layers overlying the minimal insulation regions and generating field oxide regions in the remaining portions separating the active regions. The etching is preferably carried out by a combination of dry and wet etching steps. The field oxide regions may be produced by the well known local oxidation of silicon (LOCOS).

Abstract: A method for manufacturing VLSI MOS-transistor circuits involving the production of transistors by means of a spacer layer technique and ohmic contacts from the gate interconnect to the diffused regions of the substrate (thus providing buried contacts) both being simultaneously generated. Contact holes are provided at the desired location in the substrate before the deposition of the spacer layer occurs across the surface of the substrate. The spacer layer is simultaneously structured at the side walls of the gates and at the side walls of the interconnects which serve as connections. The contact hole region is doped at the same time as the source/drain areas are provided by ion implantation. The combined manufacture of transistors using spacer technology and buried contacts makes it possible to manufacture MOS logic circuits and memory circuits with voltage stable transistors in high packing density.

Abstract: A method for etching a double layer semiconductor structure containing metal silicide layers or a metal silicide-polysilicon layer on a silicon substrate through a photoresist mask by means of reactive ion etching wherein dissociation and ionization of reactant gases take place in a plasma, the improvement which comprises:employing a mixture of chlorine gas and a highly reducing gas such as boron trichloride as the reactant gases.

Abstract: The invention provides a method of producing structures from double layers composed of a metal silicide (4) and polysilicon (3) on a silicon substrate (1) containing integrated semiconductor circuits in an operational plate reactor by reactive ion etching and with the use of a photosensitive resist mask (5) on the double layer to define desired structures. The plate reactor is provided with a controlled reactive gas mixture which contains fluorine and chlorine. The double layer (3, 4) in preferred embodiments is composed of a tantalum silicide layer and a polysilicon layer. An insulating layer (2) can be provided between the substrate and the double layer. The invention is useful for providing low-resistant interconnects in VLSI circuits.

Abstract: Polysilicon structures down to a 1 .mu.m range on substrates containing integrated semiconductor circuits are produced by plasma etching in a plate reactor with the use of SF.sub.6 and an inert gas as the reactive gas. During this process, a semiconductor crystal wafers (4, 17) covered with a SiO.sub.2 layer (16) and a polysilicon layer (15) is provided with an etch mask (14) and positioned on a grounded electrode of the plate reactor and an etching process, which achieves a high selectivity of polysilicon (15) to SiO.sub.2 (16) and to the etch mask (14), is carried out with a HF power, P, of <0.1 watt/cm.sup.2, a gas pressure, p, ranging from 60 to 120 Pa, and an electrode temperature ranging from 20.degree. to 60.degree. C. With the inventive process, large scale integrated semiconductor circuits are produced in a single stage sequence with high etching selectivity, uniform etching and a high throughput of silicon wafers.

Abstract: Circuit structures consisting of layers composed of metal silicides or metal silicide-polysilicon are produced by reactive sputter etching with sulfur hexafluoride (SF.sub.6) as the etching gas. In a practice of the invention, the etching process occurs in two steps whereby the first etching step is carried out with a high frequency power of more than 0.3 W/cm.sup.2 and the second etching step is carried out with a high frequency power of less than 0.2 W/cm.sup.2. This method is strictly anisotropic, even when a photosensitive resist is used as an etching mask, and is useful in the manufacture of fully integrated semiconductor circuits in MOS technology with metal silicide layers for reduction of the ohmic resistance of polysilicon.