Abstract: Disclosed is an improved method and system for implementing and analyzing power switch configurations. Described is a novel approach to minimize the number of power switches required for a power domain and to automatically find the locations of those power switches subject to the constraints of saturation current and maximum IR-drop on the power switches. This approach uses a fast static power consumption analysis tool to compute the current and IR drop through the power switches. The approach can apply to both column and ring style power switch insertion methodologies.

Abstract: Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

Abstract: Methods and systems provide a tool to assist a designer in selecting interconnect widths which improve both signal time propagation and maintain a reliable conductor. Downstream capacitance(s) of interconnects is evaluated, and a current which the interconnect conducts is also evaluated. The capacitance and current information is used to determine a conductor width which maintains physical reliability. The methods and systems also allow the conductor widths to be determined based upon signal propagation concerns, such that in interconnect networks where signal timing is critical, the conductor widths can be reduced while maintaining a reliable conductor.