Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

Abstract: A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.

Abstract: An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

Abstract: An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.

Abstract: A shock-absorbing mobile hard disk mounting arrangement in which shock-absorbing spring members are provided to support the hard disk on the circuit board inside the mobile hard disk box, preventing damage to the hard disk when the mobile hard disk box is vibrated accidentally.

Abstract: A mobile hard disk mounting structure is disclosed to include two bridge-like spring strips arranged in parallel inside a mobile hard disk box, each bridge-like spring strip having one end, namely, the fixed end affixed to the mobile hard disk box and the other end, namely, the free end supported on a part inside the mobile hard disk box, and a carrier plate fixedly supported on the bridge-like spring strips and having four upright studs for securing a hard disk.

Abstract: A water-resistant and floatable footwear including an outsole and insole, and an upper member affixed to the sole,wherein the footwear is floatable in water. In particular, the insole of the footwear is constructed of the material “marine buoy;” that is, the insole has an inner structure and an outer coating, the inner structure being constructed of a thermoplastic resin and the outer coating being constructed of a vinyl polymer. The footwear is advantageously water-proof and provides buoyancy in water.

Abstract: A water-resistant and floatable footwear including an outsole and insole, and an upper member affixed to the sole, wherein the footwear is floatable in water. In particular, the insole of the footwear is constructed of the material “marine buoy;” that is, the insole has an inner structure and an outer coating, the inner structure being constructed of a thermoplastic resin and the outer coating being constructed of a vinyl polymer. The footwear is advantageously water-proof and provides buoyancy in water.

Abstract: A notebook DC power sharing arrangement is disclosed to include an adapter, which has an electric socket for DC input from an external DC power supply device and an electric plug power output to a notebook computer, a DC power converter connected to the adapter through a cable for converting input DC power to a predetermined voltage level, and a power cable extended from the DC power converter for power output to an external peripheral apparatus.

Abstract: An indicator circuit arrangement of a transmission cable for connecting a peripheral apparatus to a computer is disclosed to have a cord-like electroluminescent lamp axially extended in the cable between the electric connectors at the ends of the cable, and a detector and converter circuit installed in one electric connector and adapted to detect the connection status of the cable between the computer and the peripheral apparatus and to drive on the cord-like electroluminescent lamp upon normal connection of the cable between the computer and the peripheral apparatus.

Abstract: A transmission cable for connecting a peripheral apparatus to a computer is disclosed to have a cord-like electroluminescent lamp axially extended in the cable between the electric connectors at the ends of the cable, and a detecting and starting circuit installed in the cable and adapted to detect the connection status of the cable between the computer and the peripheral apparatus and to drive on the cord-like electroluminescent lamp upon normal connection of the cable between the computer and the peripheral apparatus.

Abstract: A transmission cable for connecting a peripheral apparatus to a computer is disclosed to have a cord-like electroluminescent lamp axially extended in the cable between the electric connectors at the ends of the cable, and a detecting and starting circuit installed in the cable and adapted to detect the connection status of the cable between the computer and the peripheral apparatus and to drive on the cord-like electroluminescent lamp upon normal connection of the cable between the computer and the peripheral apparatus.

Abstract: An indicator circuit arrangement of a transmission cable for connecting a peripheral apparatus to a computer is disclosed to have a cord-like electroluminescent lamp axially extended in the cable between the electric connectors at the ends of the cable, and a detector and converter circuit installed in one electric connector and adapted to detect the connection status of the cable between the computer and the peripheral apparatus and to drive on the cord-like electroluminescent lamp upon normal connection of the cable between the computer and the peripheral apparatus.

Abstract: A network cable capable of obtaining the necessary working power supply for its internal control circuit that detects the connection and transmission status of the transmission line and drives an indicator light to give a visual indication signal indicative of the detection result.

Abstract: A CPU cooling structure is constructed having a thermoelectric cooling panel installed in a heat sink and controlled by a control circuit to cool the CPU to which the heat sink is fastened.

Abstract: A CPU cooling structure is constructed having a thermoelectric cooling panel installed in a heat sink and controlled by a control circuit to cool the CPU to which the heat sink is fastened.

Abstract: A transmission cable having a cable and two connectors at the ends of the cable is disclosed to include an integrated circuit and a LED in the transparent plastic housing of each connector. The integrated circuit drives the LED to emit light after installation of the transmission cable, and drives the LED to flash upon transmission of signal/data through the cable. The LED is off when the transmission cable failed.