Abstract: An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.

Abstract: A method of optimizing a bond out design includes steps of: (a) receiving as input an initial bond out design including at least one selected I/O pad and a top redistribution layer; (b) determining whether to include a lower redistribution layer in an optimized bond out design; (c) selecting a trace design to be included in the optimized bond out design for connecting the selected I/O pad to the top redistribution layer according to a bump function of the selected I/O pad; and (d) generating as output the optimized bond out design.

Abstract: A method of optimizing a bond out design includes steps of: (a) receiving as input an initial bond out design including at least one selected I/O pad and a top redistribution layer; (b) determining whether to include a lower redistribution layer in an optimized bond out design; (c) selecting a trace design to be included in the optimized bond out design for connecting the selected I/O pad to the top redistribution layer according to a bump function of the selected I/O pad; and (d) generating as output the optimized bond out design.