Abstract: A consumer product or toy suction cup ensemble includes a housing, a suction cup formation, and a relief valve formation. A collar element may be included in certain embodiments. The housing includes a stem-letting aperture. The suction cup formation includes a collapsible cup portion and a stem portion. The stem portion includes a valve-letting passage. The stem-letting aperture receives the stem section. The relief valve formation includes a valve stem and a valve upper portion. The valve stem includes opposed valve stem grooves that extend from a valve stem end and have a groove length lesser than the valve stem thereby forming a valve-sealing portion. The valve stem is receivable in the valve-letting passage. The collar element of certain embodiments includes an outer collar periphery and an inner slot portion. The inner slot portion accepts the collar-receiving stem section and the outer collar periphery is wider than stem-letting aperture.

Abstract: A consumer product or toy suction cup ensemble includes a housing, a suction cup formation, and a relief valve formation. A collar element may be included in certain embodiments. The housing includes a stem-letting aperture. The suction cup formation includes a collapsible cup portion and a stem portion. The stem portion includes a valve-letting passage. The stem-letting aperture receives the stem section. The relief valve formation includes a valve stem and a valve upper portion. The valve stem includes opposed valve stem grooves that extend from a valve stem end and have a groove length lesser than the valve stem thereby forming a valve-sealing portion. The valve stem is receivable in the valve-letting passage. The collar element of certain embodiments includes an outer collar periphery and an inner slot portion. The inner slot portion accepts the collar-receiving stem section and the outer collar periphery is wider than stem-letting aperture.

Abstract: According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly from a next processing element in the series.

Abstract: In general, in one aspect, the disclosure describes a processor that includes a memory to store at least a portion of instructions of at least one program and multiple packet engines that include an engine instruction cache to store a subset of the at least one program. The processor also includes circuitry coupled to the packet engines and the memory to receive requests from the multiple engines for subsets of the at least one portion of the at least one set of instructions.

Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and a set of multiple engines coupled to the instruction store. The engines include an engine instruction cache and circuitry to request a subset of the at least the portion of the at least one program.

Abstract: Systems and methods for scalable packet buffer descriptor management in ATM-Ethernet bridge gateways are disclosed. An ATM-Ethernet processor interfacing between an ATM processor and an Ethernet network processor generally includes a packet buffer pointer ring containing ATM processor packet buffer pointers for managing traffic from the Ethernet network processor to the ATM processor, and a packet descriptor ring and a data buffer for managing traffic from the ATM processor to the Ethernet network processor. The packet descriptor ring contains packet descriptors each including an ATM-Ethernet packet buffer memory address in the data buffer. The ATM processor may be in communication with a SONET framer while the Ethernet network processor may be in communication with an Ethernet MAC.

Abstract: A method of executing instructions on a processor includes, receiving a first condition code produced by executing a first instruction during a first clock cycle on an array of engines included in the processor, receiving a second condition code produced by executing a second instruction during a second clock cycle on the array of engines included in the processor, and executing a logical operator on the first and second condition codes during the second clock cycle on the array of engines included in the processor.