Abstract: An optical tunable laser design for the optical telecommunication industry is disclosed in this invention. This new design is economical, reliable, robust and with superior optical performances. The design offers broadband tunability, high output power, narrow laser line-width and high SMSR. And in addition, the tunable laser is distinguishable from conventional designs by the mere facts that there are no moving parts, therefore, making it very reliable, and the tuning method of this invention is non-thermal and non-mechanical making its tuning very fast in the sub-millisecond range. In the manufacturing front, it is low cost and easy to produce. It can be achieved with automation equipment like those used in the IC placement and PC assembly industry, therefore, the products as that disclosed in this invention can be provided with significantly reduced production costs and marketed with very competitive price.

Abstract: An optical tunable laser design for the optical telecommunication industry is disclosed in this invention. This new design is economical, reliable, robust and with superior optical performances. The design offers broadband tunability, high output power, narrow laser line-width and high SMSR. And in addition, the tunable laser is distinguishable from conventional designs by the mere facts that there are no moving parts, therefore, making it very reliable, and the tuning method of this invention is non-thermal and non-mechanical making its tuning very fast in the sub-millisecond range. In the manufacturing front, it is low cost and easy to produce. It can be achieved with automation equipment like those used in the IC placement and PC assembly industry, therefore, the products as that disclosed in this invention can be provided with significantly reduced production costs and marketed with very competitive price.

Abstract: There is shown and described a floating point processor having improved architecture and configuration. The floating point processor (FPP) performs addition, subtraction, multiplication, division and square root operations. Usually, the square root operation is not built into the FPP hardware because of the increased complexity of the design, and, therefore, cost of the goods. Rather, the square root operation is usually implemented by firmware or software. The device of this invention performs the floating point square root operation in hardware rather than in software or firmware while adding very little additional hardware to existing circuitry which is required for the basic addition, subtraction, multiplication and division operations. In addition, the operations are performed as rapidly as, or more rapidly than, prior art devices.

Abstract: There is disclosed a circuit which is capable of performing a square root function in a floating point processor in such a manner that the speed of operation is increased by approximately 50%.

Abstract: There is described a floating point processor architecture which permits multiple bit shifting over strings of binary 1's and strings of binary O's in a single machine cycle. During a multiply operation, an MQ register (arranged in parallel) which stored the multiplier, shifts the multiplier out for decoding at a rate comparable to the rate at which the partial product is shifted. This is made possible by using a parallel MQ register so that two bits may be shifted per clock cycle. This architecture permits extremely fast multiplication by using a multiple bit shift architecture while minimizing hardware requirements.