Abstract: There is provided a circuit and method for subtracting floating point numbers which are represented by binary bits. In this circuit, the smaller number (minuend) in one register is arranged so that the complement thereof is denormalized and added to the subtrahend (i.e. larger number) and the result of the addition is returned to the original register. At that time, the signal stored in the register is renormalized. In this circuit, the number of guard bits required to guarantee round off accuracy is only two.

Abstract: This invention is directed at an apparatus and method for detecting zero operand information and which also serves to detect trailing zeros. This circuit has application in computer circuitry, systems or the like wherein elongated information trains represented by multiple words of multiple bits are multiplied by equally long information trains. In many cases, the trains comprise a plurality of trailing zeros which, in accordance with the operation of this circuit, can be detected whereby the multiplication operation can be significantly speeded by avoiding unnecessary multiplication by zeros without loss of accuracy.