Patents by Inventor Wilson Y. Liao

Wilson Y. Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache
    Patent number: 8087024
    Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Wilson Y. Liao, Prashant R. Chandra, Jeen-Yuan Miin, Yim Pun
  • Thread-based engine cache partitioning
    Patent number: 7536692
    Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Wilson Y. Liao, Prashant R. Chandra, Jeen-Yuan Miin, Yim Pun
  • Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache
    Publication number: 20090089546
    Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
    Type: Application
    Filed: November 18, 2008
    Publication date: April 2, 2009
    Applicant: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Wilson Y. Liao, Prashant R. Chandra, Jeen-Yuan Miin, Yim Pun
  • Processing element with next and previous neighbor registers for direct data transfer
    Patent number: 7275145
    Abstract: According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly from a next processing element in the series.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: September 25, 2007
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Prashant Chandra, Wilson Y. Liao, Jeen-Yuan Miin, Pun Yim, Chen-Chi Kuo, Jaroslaw J. Sydir
  • Method and process for scheduling data packet collection
    Publication number: 20040252687
    Abstract: A method executed in a computing device for scheduling data packet transfer, the method includes receiving a first and second bit, the first bit indicates if a first digital device is ready to transfer a first data packet, the second bit indicates if a second digital device is ready to transfer a second data packet, receiving a binary number that identifies the first bit, determining the first digital device is ready to transfer the first data packet based on the binary number identifying the first bit, and incrementing the binary number to identify the second bit.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Inventors: Sridhar Lakshmanamurthy, Prashant R. Chandra, Wilson Y. Liao, Jeen-Yuan Miin, Yim Pun, Chen-Chi Kuo, Jaroslaw J. Sydir