Abstract: A high density capacitor 12, a method of manufacturing it, and applications of it are described. The capacitor 12 is an electrochemical capacitor using a metal ion accepting cathode 22 and a metal ion accepting anode 26 and a amorphous solid electrolyte 24 between. The cathode and anode may be of amorphous lithium ion intercalating material such as suitable transition metal oxides with multiple oxidation states.

Abstract: There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapor deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.

Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.

Abstract: A high density capacitor 12, a method of manufacturing it, and applications of it are described. The capacitor 12 is an electrochemical capacitor using a metal ion accepting cathode 22 and a metal ion accepting anode 26 and a amorphous solid electrolyte 24 between. The cathode and anode may be of amorphous lithium ion intercalating material such as suitable transition metal oxides with multiple oxidation states.

Abstract: There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.

Abstract: A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).

Abstract: A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).

Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.

Abstract: There is described a method of forming a barrier layer (6, 110) over a surface of a copper line (3, 107) embedded in a dielectric material (2, 100) in an interconnect structure for a semiconductor device. The barrier layer (6, 110) is selectively deposited over the surface of the copper line (3, 107) by a vapour deposition step and the surface of the dielectric material (2, 100) is treated prior to the vapour deposition step to inhibit deposition of the barrier layer (6, 110) there on during the vapour deposition step. Preferably, the vapour deposition step comprises atomic layer deposition.

Abstract: A method of forming a capping layer on a copper interconnect line (14). The method comprises providing a layer (20) of Aluminium over the interconnect line (14) and the dielectric layer (10) in which it is embedded. This may be achieved by deposition or chemical exposure. The structure is then subjected to a process, such as annealing or further chemical exposure, in an environment containing, for example, Nitrogen atoms, so as to cause indiffusion of Al into the copper line (14) and nitridation to form a diffusion barrier 26 of the intermetallic compound CuAlN.

Abstract: There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapour deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.

Abstract: There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.