Abstract: A circuit capable of handling picture-in-picture, high resolution double window, multi-picture-in-picture with a vertically compressed live main picture and with a live, a long picture-in-picture repay, and scan rate conversion, the circuit comprising first (SUB1) and second (SUB2) field memories for storing and processing a sub video signal (AN SUB, DIG SUB), and an output field memory (MN) for combining outputs of the first (SUB1) and second (SUB2) field memories with a main video signal (AN MN, DIG MN). Preferably, smart switching (LD1, LD2) is used to switch a field memory (SUB2) between compression of the main picture and PIP replay depending on the specification point required.