Patents by Inventor Wim Y. Deweerd
Wim Y. Deweerd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8975633Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.Type: GrantFiled: October 31, 2012Date of Patent: March 10, 2015Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
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Patent number: 8940463Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.Type: GrantFiled: March 14, 2013Date of Patent: January 27, 2015Assignee: Intermolecular, Inc.Inventor: Wim Y. Deweerd
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Patent number: 8936889Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.Type: GrantFiled: March 14, 2013Date of Patent: January 20, 2015Assignee: Intermolecular, Inc.Inventor: Wim Y. Deweerd
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Patent number: 8741712Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.Type: GrantFiled: September 18, 2012Date of Patent: June 3, 2014Assignees: Intermolecular, Inc., Elpidia Memory, Inc.Inventors: Tony P. Chiang, Wim Y. Deweerd, Sandra G Malhotra
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Patent number: 8679939Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (<2 nm) or highly doped so that it remains amorphous after subsequent anneal treatments. A second dielectric material is formed above the first dielectric material. The second dielectric material is sufficiently thick (>3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.Type: GrantFiled: January 9, 2013Date of Patent: March 25, 2014Assignee: Intermolecular, Inc.Inventors: Sandra Malhotra, Wim Y. Deweerd, Hiroyuki Ode
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Publication number: 20140080282Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.Type: ApplicationFiled: September 18, 2012Publication date: March 20, 2014Applicants: Elpida Memory, Inc., Intermolecular, Inc.Inventors: Tony P. Chiang, Wim Y. Deweerd, Sandra G. Malhotra
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Publication number: 20140077336Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.Type: ApplicationFiled: January 9, 2013Publication date: March 20, 2014Applicant: INTERMOLECULAR INC.Inventors: Tony P. Chiang, Wim Y. Deweerd, Sandra G. Malhotra
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Patent number: 8652927Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.Type: GrantFiled: January 10, 2013Date of Patent: February 18, 2014Assignee: Intermolecular, Inc.Inventors: Sandra Malhotra, Hanhong Chen, Wim Y. Deweerd, Edward L. Haywood, Hiroyuki Ode, Gerald Richardson
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Patent number: 8647943Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode materials are conductive molybdenum oxide.Type: GrantFiled: June 12, 2012Date of Patent: February 11, 2014Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Hanhong Chen, Wim Y. Deweerd, Edward L Haywood, Sandra G Malhotra, Hiroyuki Ode
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Publication number: 20130328168Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (<2nm) or highly doped so that it remains amorphous after subsequent anneal treatments. A second dielectric material is formed above the first dielectric material. The second dielectric material is sufficiently thick (>3nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.Type: ApplicationFiled: January 9, 2013Publication date: December 12, 2013Applicant: INTERMOLECULAR INC.Inventors: Sandra G. Malhotra, Wim Y. Deweerd, Hiroyuki Ode
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Publication number: 20130320495Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.Type: ApplicationFiled: January 10, 2013Publication date: December 5, 2013Applicant: INTERMOLECULAR, INC.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Edward L. Haywood, Hiroyuki Ode, Gerald Richardson
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Patent number: 8574999Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.Type: GrantFiled: January 10, 2013Date of Patent: November 5, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
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Patent number: 8569818Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.Type: GrantFiled: October 23, 2012Date of Patent: October 29, 2013Assignee: Intermolecular, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
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Patent number: 8542523Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.Type: GrantFiled: January 10, 2013Date of Patent: September 24, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Karthik Ramani, Wim Y. Deweerd, Hiroyuki Ode
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Patent number: 8541868Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.Type: GrantFiled: October 31, 2012Date of Patent: September 24, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
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Patent number: 8541283Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.Type: GrantFiled: March 14, 2013Date of Patent: September 24, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Mitsuhiro Horikawa, Kenichi Koyanagi, Hiroyuki Ode, Xiangxin Rui
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Patent number: 8530348Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.Type: GrantFiled: May 29, 2012Date of Patent: September 10, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Edward L. Haywood, Hiroyuki Ode, Gerald Richardson
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Patent number: 7939815Abstract: By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.Type: GrantFiled: December 30, 2008Date of Patent: May 10, 2011Assignee: STMicroelectronics S.r.l.Inventors: Jinwook Lee, Kuo-wei Chang, Jason S. Reid, Wim Y. Deweerd, Aleshandre M. Diaz
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Publication number: 20100163818Abstract: By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: STMicroelectronics S.r.l.Inventors: Jinwook Lee, Kuo-wei Chang, Jason S. Reid, Wim Y. Deweerd, Aleshandre M. Diaz