Patents by Inventor Win Hung

Win Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MOS devices with improved source/drain regions with SiGe
    Patent number: 8569846
    Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wei-Hua Hsu, Yu-En Percy Chang, Chung Li Chang, Chi-Feng Cheng, Win Hung, Kishimoto Ko
  • MOS Devices with Improved Source/Drain Regions with SiGe
    Publication number: 20110256681
    Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.
    Type: Application
    Filed: June 22, 2011
    Publication date: October 20, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wei-Hua Hsu, Yu-En Percy Chang, Chung Li Chang, Chi-Feng Cheng, Win Hung, Kishimoto Ko
  • MOS devices with improved source/drain regions with SiGe
    Patent number: 7989901
    Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: August 2, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wei-Hua Hsu, Yu-En Percy Chang, Chung Li Chang, Chi-Feng Cheng, Win Hung, Kishimoto Ko
  • MOS devices with improved source/drain regions with SiGe
    Publication number: 20080265256
    Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Inventors: Chun-Chieh Lin, Wei-Hua Hsu, Yu-En Percy Chang, Chung Li Chang, Chi-Feng Cheng, Win Hung, Kishimoto Ko
  • Method of automatically creating a semiconductor processing prober device file
    Patent number: 7271609
    Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kevin Liao, Edward Chen, Win Hung, Jumbo Chuang, Chang-Chi Hsu, Chia-Ping Liu, Chun-Chieh Hsiao
  • Method of Automatically Creating a Semiconductor Processing Prober Device File
    Publication number: 20060255824
    Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.
    Type: Application
    Filed: May 16, 2005
    Publication date: November 16, 2006
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kevin Liao, Edward Chen, Win Hung, Jumbo Chuang, Chang-Chi Hsu, Chia-Ping Liu, Chun-Chieh Hsiao