Patents by Inventor Win Naing
Win Naing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045819Abstract: In some examples, an apparatus includes a circuit configured to receive communication on a first bus. The circuit is also configured to provide the communication on a second bus for a first period of time. The circuit is also configured to monitor a duration of the providing of the communication on the second bus. The circuit is also configured to, responsive to the duration exceeding a threshold amount, stop providing the communication on the second bus for a second period of time.Type: ApplicationFiled: March 31, 2023Publication date: February 8, 2024Inventors: Suzanne M. VINING, Julie NIRCHI, Win Naing MAUNG, Douglas E. WENTE
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Publication number: 20230412211Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: ApplicationFiled: September 6, 2023Publication date: December 21, 2023Inventors: Suzanne Mary VINING, Gary CHARD, Win Naing MAUNG, Mark Alan McADAMS
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Patent number: 11791863Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: GrantFiled: August 27, 2021Date of Patent: October 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suzanne Mary Vining, Gary Chard, Win Naing Maung, Mark Alan McAdams
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Patent number: 11580053Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.Type: GrantFiled: June 15, 2021Date of Patent: February 14, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Win Naing Maung, Suzanne Mary Vining, Yonghui Tang, Douglas Edward Wente, Huanzhang Huang
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Patent number: 11543875Abstract: In an example, a data communication device includes one or more receivers, and one or more transmitters. The data communication device detects a start of frame packet (?SOF) on a data bus, wherein the ?SOF indicates the start of a microframe; determines whether there are any data packets contained in the microframe during a first threshold period after the ?SOF; and detects that there is no data packet contained in the microframe during the first threshold period after the ?SOF, and in response, transitions at least one of the one or more transmitters from an active state to an OFF state, and transitions the at least one of the one or more transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe.Type: GrantFiled: January 18, 2022Date of Patent: January 3, 2023Assignee: Texas Instruments IncorporatedInventors: Suzanne Mary Vining, Douglas Edward Wente, Win Naing Maung, Julie Marie Nirchi
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Patent number: 11436173Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: GrantFiled: April 19, 2021Date of Patent: September 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Win Naing Maung, Bhupendra Sharma, Huanzhang Huang, Douglas Edward Wente, Suzanne Mary Vining, Mustafa Ulvi Erdogan
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Publication number: 20220224335Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.Type: ApplicationFiled: March 21, 2022Publication date: July 14, 2022Inventors: Win Naing Maung, Bharath Kumar Singareddy, Soumi Paul, Mayank Garg, Suzanne Mary Vining
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Patent number: 11386036Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.Type: GrantFiled: May 6, 2019Date of Patent: July 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Win Naing Maung, Saurabh Goyal, Bhupendra Sharma, Huanzhang Huang, Douglas Edward Wente, Suzanne Mary Vining, Mustafa Ulvi Erdogan
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Patent number: 11356236Abstract: Circuit including a first port to couple to a first device; a second port to couple to a second device; a first channel having an input coupled to first port and an output coupled to second port, the first channel to re-drive a signal and output re-driven signal; a second channel having an input coupled to second port and an output coupled to first port, the second channel to re-drive a signal and output re-driven signal; and a controller to: enable first channel and disable second channel responsive to detecting a signal edge at first port; enable second channel and disable first channel responsive to detecting a signal edge at second port; sample impedance at first port if signal received at first port is de-asserted while first channel is enabled; and sample impedance at second port if signal received at second port is de-asserted while second channel is enabled.Type: GrantFiled: March 23, 2020Date of Patent: June 7, 2022Assignee: Texas Instruments IncorporatedInventors: Win Naing Maung, Charles Michael Campbell
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Publication number: 20220137695Abstract: In an example, a data communication device includes one or more receivers, and one or more transmitters. The data communication device detects a start of frame packet (?SOF) on a data bus, wherein the ?SOF indicates the start of a microframe; determines whether there are any data packets contained in the microframe during a first threshold period after the ?SOF; and detects that there is no data packet contained in the microframe during the first threshold period after the ?SOF, and in response, transitions at least one of the one or more transmitters from an active state to an OFF state, and transitions the at least one of the one or more transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Inventors: Suzanne Mary Vining, Douglas Edward Wente, Win Naing Maung, Julie Marie Nirchi
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Patent number: 11309892Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.Type: GrantFiled: February 11, 2021Date of Patent: April 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Win Naing Maung, Bharath Kumar Singareddy, Soumi Paul, Mayank Garg, Suzanne Mary Vining
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Publication number: 20220100689Abstract: An embedded USB2 (eUSB2) repeater includes an eUSB2 port having first and second terminals. The eUSB2 port facilitates two-way communication between the repeater and an application processor unit (APU) according to voltage level specifications for eUSB2. The repeater includes a USB port having first and second terminals. The USB port facilitates two-way communication between the repeater and a Universal Asynchronous Receiver Transmitter (UART) according to voltage level specifications for US. The repeater includes a multiplexer having an input coupled to receive a control signal. The multiplexer selectively establishes connections between the first and second terminals of the eUSB2 port and the first and second terminals of the USB port.Type: ApplicationFiled: September 1, 2021Publication date: March 31, 2022Inventors: Suzanne Mary Vining, Win Naing Maung
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Patent number: 11281284Abstract: A method includes detecting a micro start of frame packet (?SOF) on a data bus. If there is at least one data packet contained in a microframe during the first threshold period after the ?SOF, transmitters are held in an active state. If there is no data packet in the first threshold period after the ?SOF, the transmitters are transitioned from the active state to an OFF state. The method also includes transitioning the transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe. The method also includes transitioning the transmitters from the OFF state to the active state if a data packet is received in the OFF state. The method also includes dropping the data packet received in the OFF state and transitioning from the OFF state to the active state when the data packet is dropped.Type: GrantFiled: December 17, 2019Date of Patent: March 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suzanne Mary Vining, Douglas Edward Wente, Win Naing Maung, Julie Marie Nirchi
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Publication number: 20210391893Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: Suzanne Mary VINING, Gary CHARD, Win Naing MAUNG, Mark Alan McADAMS
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Publication number: 20210311902Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.Type: ApplicationFiled: June 16, 2021Publication date: October 7, 2021Inventors: Win Naing MAUNG, Suzanne Mary VINING
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Publication number: 20210311898Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.Type: ApplicationFiled: June 15, 2021Publication date: October 7, 2021Inventors: Win Naing MAUNG, Yonghui TANG, Huanzhang HUANG, Douglas Edward WENTE
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Publication number: 20210311903Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.Type: ApplicationFiled: June 15, 2021Publication date: October 7, 2021Inventors: Win Naing MAUNG, Suzanne Mary VINING, Yonghui TANG, Douglas Edward WENTE, Huanzhang HUANG
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Patent number: 11133841Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: GrantFiled: January 31, 2020Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suzanne Mary Vining, Gary Chard, Win Naing Maung, Mark Alan McAdams
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Publication number: 20210250026Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.Type: ApplicationFiled: February 11, 2021Publication date: August 12, 2021Inventors: Win Naing Maung, Bharath Kumar Singareddy, Soumi Paul, Mayank Garg, Suzanne Mary Vining
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Publication number: 20210240648Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Inventors: Win Naing MAUNG, Bhupendra SHARMA, Huanzhang HUANG, Douglas Edward WENTE, Suzanne Mary VINING, Mustafa Ulvi ERDOGAN