Abstract: In a phase matching circuit for generating a system clock signal for an incoming data signal from a locally existing clock signal, a delay signal is calculated from the detected phase position of the data signal in that a memory addressed with the detected phase position outputs an allocated delay signal. In a specific embodiment, the memory is supplied with an address that is compensated by the most recently identified delay. In a further development, a control comprising the memory shares circuits for a number of data signals. The phase matching, which automatically recognizes a jitter compatibility more suitable for the clocking than the jitter compatibility employed at the moment, can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.

Abstract: A control system for controlling access to a bus (BU) by a unit (P) connected to the bus (BU), including a ring circuit in which a monoflop function element and one or more coupling elements are connected in-line, each coupling element associated with a respective unit. For controlling access, a logic signal of a first type is supplied into the ring by the monoflop function element, the logic signal being successively conducted via the coupling elements to the units seeking access to the bus. Access to the bus is only allowed when the coupling element senses a transition from a logic state of the first type to a logic state of a second type at its ring circuit input.

Abstract: The logical operation of binary input signals can be carried out with a programmable circuit arrangement. It contains a matrix (MA) of crossing data lines (DL) and coupling lines (KL) at whose coupling locations switching elements (KE) are arranged corresponding to a function table to be realized. The switching elements (KE) can assume three statuses: one status corresponds to a binary 1 and the second status corresponds to a binary 0; the third status corresponds to a binary 1 or to a binary 0. Every data line (DL) can be operated as input or as output with the assistance of a control signal (ST) that is supplied to an input circuit and to an output circuit (AG). The input signals coupled from the data lines operated as input onto a coupling line (KL) are subjected to an AND operation on the coupling line. By contrast, the signals coupled from the coupling lines (KL) onto a data line (DL) wired as output are subjected to an OR operation on the data line.

Abstract: Circuit arrangements (ULB) can be connected to one another with the assistance of a connection network (VN). Every circuit arrangement (ULB) can thereby operate as transmitter or as receiver. The connection network (VN) contains a matrix that is composed of a connection matrix and of an adjustment matrix. In the connection matrix, the data lines (DL) leading to the circuit arrangements (ULB) cross with coupling lines, whereby switching elements are arranged at the crossing locations. The adjustment matrix is composed of adjustment lines that cross with the coupling lines, whereby switching elements are arranged at the crossing locations. The connections between the data lines can be determined by programming the switching elements in the connection matrix and in the adjustment matrix and by applying an adjustment code to the adjustment matrix. The assistance of control signals can thereby be used to determine whether the data lines represent a data input or a data output.

Abstract: A programmable circuit for carrying out logic operations on binary input signals. The programmable circuit contains a matrix of first lines crossed with second lines thereby defining intersections at which logic units corresponding to a function table are connected. Two of the first lines are combined to form a line pair. The matrix is programmed in that a logic unit is connected between one of the lines of the line pair and a second line for the binary value of "1" and a logic unit is connected between the other of the lines of the line pair and the second line for programming a binary value of "0". Utilizing control signals, the logic units can be activated either in one direction or the other. Therefore, it is thus possible to set a line pair either as an input or as an output of the programmable circuit. When a line pair acts as an input, the binary signals coupled into the second lines by the logic units are subjected to an AND operation on the second lines.