Abstract: In order to provide a method of determining the signal strength in a receiver or transmitter with complex signal processing using the in-phase channel (I channel) and the quadrature channel (Q channel), by means of which it is also possible to reliably determine the signal strength in receivers with a low intermediate frequency, it is proposed that the field strength signals of the I channel and of the Q channel are fed to an evaluation unit and that, in the evaluation unit, an overall field strength signal is generated on a logarithmic scale without intermediate frequency residues from the individual field strength signals.

Abstract: Circuit arrangement for generating a control signal. A circuit arrangement for generating a control signal for a controllable oscillator of a receiving device, is arranged to mix an FSK modulated input signal, having at least two predetermined input frequencies, with an oscillation, output by a controllable oscillator, so as to form an intermediate frequency signal, as well as to derive from the intermediate frequency signal a data signal whose instantaneous value is determined by the frequency of the intermediate frequency signal (intermediate frequency) and also a demodulator pulse signal whose frequency and/or phase is a measure of the frequency and/or phase of the intermediate frequency signal, from the intermediate frequency signal.

Abstract: A description is given of a circuit arrangement comprisinga filter quadripole having two output terminals anda voltage follower circuit having two terminals, said terminals having identical electric potentials when the voltage follower circuit is in its turned-on state, each of the terminals of the voltage follower circuit being connected to one of the output terminals of the filter quadripole respectively, and the voltage follower circuit only being in its turned-on state during the turn-on time interval of the circuit arrangement. This circuit arrangement is suitable for a receiver circuit, more particularly, for a pager and has a very brief turn-on time.

Abstract: A phase comparison circuit includes a double balanced mixer stage which receives a sine signal as well as this sine signal in anti-phase and a square-wave switching signal of the same nominal frequency, two active current mirror circuits are used which incorporate at least two common negative feedback circuit elements, the first of which is operative in the input-sided negative feedback of the first current mirror circuit and in the output-sided negative feedback of the second current mirror circuit and the second of which is operative in the reverse way. The two current mirror circuits are alternately connected to the two balanced mixer stages by means of a switching stage during the half cycle clock of the switching signal.

Abstract: An approximately sinusoidal signal is generated by superimposing a first signal, which has a half cycle duration and corresponds to a triangular signal which is suppressed during every second half cycle, on a second triangular signal, every second waveform of the superimposed signal thus obtained being inverted.

Abstract: An FM receiver for demodulating an RF carrier signal containing a pilot frequency signal is provided. The receiver includes first and second frequency control loops. The first frequency control loop selects the local oscillator signal frequency. The reference signal oscillator in the first frequency control loop forms a part of a second frequency control loop. The second frequency control loop locks the phase of the reference signal oscillator with a detected pilot signal. In this way, the tuning signal of the local oscillator is kept phase locked to the detected pilot signal. Additional provisions are provided for changing the divisor of the second phase lock loop such that the time for establishing phase lock is reduced.

Abstract: A receiver for AM signals, in which the carrier is amplitude modulated with a first signal (L+R) and phase modulated with a second signal (L-R), includes a circuit for reducing distortion in the output signal due to amplitude overmodulation. This circuit includes an overmodulation detector for controlling a switch in a phase demodulation signal channel, which switch, coupled between a demodulator and an integrator in this signal channel, effectively short-circuits the input to the integrator causing the output thereof to remain constant for the duration of the overmodulation.

Abstract: In the circuit according to the invention the entire FM-demodulator output signal is evaluated, that is to say the sum of the low-frequency signal and the d.c. voltage (AFC) component. The absolute value is produced therefrom and an attenuator circuit becomes operative in the low-frequency channel when the absolute value of the demodulator output signal exceeds a predetermined threshold value. This not only enables the suppression of spurious receptions, but also the suppression of intermediate receptions (the reception of two transmitters on the filter edges) and surging of noise. The circuit can be easily implemented in integrated circuit technique.