Patents by Inventor Winfried W. Wilcke
Winfried W. Wilcke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10671910Abstract: A connectivity look up structure is maintained for a network that comprises a plurality of nodes, each node is connectable to one or more other nodes, and nodes that are connected tend to be local to one another in the network, and the number of node connections in the network tends to be sparse in relation to the number of potential node connections in the network. The connectivity look up structure stores, for a given node, an address of each other node that is connected to the given node, wherein the stored address for the other node is represented as a run-length encoded difference between a full network address of the given node and a full network address of the other node.Type: GrantFiled: December 7, 2015Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Arvind Kumar, Winfried W. Wilcke
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Patent number: 10613754Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: GrantFiled: October 9, 2019Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Publication number: 20200042182Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: ApplicationFiled: October 9, 2019Publication date: February 6, 2020Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Patent number: 10546809Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.Type: GrantFiled: October 3, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles E. Cox, Harald Huels, Arvind Kumar, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke
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Patent number: 10503402Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: GrantFiled: December 27, 2017Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Patent number: 10423877Abstract: Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.Type: GrantFiled: August 15, 2016Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles E. Cox, Harald Huels, Arvind Kumar, Pritish Narayanan, Ahmet S. Ozcan, J. Campbell Scott, Winfried W. Wilcke
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Publication number: 20190035722Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.Type: ApplicationFiled: October 3, 2018Publication date: January 31, 2019Inventors: Charles E. Cox, Harald Huels, Arvind Kumar, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke
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Patent number: 10147676Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.Type: GrantFiled: May 15, 2017Date of Patent: December 4, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles E. Cox, Harald Huels, Arvind Kumar, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke
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Publication number: 20180331028Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.Type: ApplicationFiled: May 15, 2017Publication date: November 15, 2018Inventors: Charles E. Cox, Harald Huels, Arvind Kumar, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke
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Publication number: 20180136846Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: ApplicationFiled: December 27, 2017Publication date: May 17, 2018Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Publication number: 20180046908Abstract: Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.Type: ApplicationFiled: August 15, 2016Publication date: February 15, 2018Inventors: Charles E. Cox, Harald Huels, Arvind Kumar, Pritish Narayanan, Ahmet S. Ozcan, J. Campbell Scott, Winfried W. Wilcke
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Patent number: 9886193Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: GrantFiled: May 15, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Publication number: 20170161605Abstract: A connectivity look up structure is maintained for a network that comprises a plurality of nodes, each node is connectable to one or more other nodes, and nodes that are connected tend to be local to one another in the network, and the number of node connections in the network tends to be sparse in relation to the number of potential node connections in the network. The connectivity look up structure stores, for a given node, an address of each other node that is connected to the given node, wherein the stored address for the other node is represented as a run-length encoded difference between a full network address of the given node and a full network address of the other node.Type: ApplicationFiled: December 7, 2015Publication date: June 8, 2017Inventors: Arvind Kumar, Winfried W. Wilcke
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Publication number: 20160334991Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
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Patent number: 8289830Abstract: A method and apparatus for storing data is provided. One implementation involves providing a fiber medium for storing data, wherein the fiber medium has a characteristic configured to irreversibly change when exposed to write irradiation. The fiber medium is logically partitioned into cells along the length of the fiber medium. Data is stored in a cell of the fiber medium by exposing the cell to write irradiation to irreversibly change characteristic of the bulk of the cell.Type: GrantFiled: December 16, 2009Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Ralph A. Becker-Szendy, Winfried W. Wilcke
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Publication number: 20110141871Abstract: A method and apparatus for storing data is provided. One implementation involves providing a fiber medium for storing data, wherein the fiber medium has a characteristic configured to irreversibly change when exposed to write irradiation. The fiber medium is logically partitioned into cells along the length of the fiber medium. Data is stored in a cell of the fiber medium by exposing the cell to write irradiation to irreversibly change characteristic of the bulk of the cell.Type: ApplicationFiled: December 16, 2009Publication date: June 16, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ralph A. Becker-Szendy, Winfried W. Wilcke
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Publication number: 20110122527Abstract: Embodiments of the invention relate to storing and locating a self-describing storage cartridge. An aspect of the invention includes a system for storing and locating a self-describing storage cartridge. The system includes a storage cartridge. The storage cartridge includes a first storage module configured to store data objects. The storage cartridge further includes a second storage module configured to store an index describing the data objects stored on the first storage module. The storage cartridge further includes a connector coupled to the second storage module and configured to provide an external device with access to the second storage module.Type: ApplicationFiled: November 25, 2009Publication date: May 26, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Arnon Amir, Edwin R. Childers, Wayne I. Imaino, Winfried W. Wilcke
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Publication number: 20080238582Abstract: A flexible capacitive coupler assembly includes a flexible dielectric substrate assembly having a front surface and a rear surface, the front surface having thereon a macroscopic metal capacitive pad. A package supports the flexible dielectric substrate. An electrical connection is made to package wiring or leads on the flexible dielectric substrate to establish electrical contact with a computer subsystem.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Applicant: International Business Machines CorporationInventors: Steven A. Cordes, Matthew J. Farinelli, Robert B. Garner, Winfried W. Wilcke
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Patent number: 7385457Abstract: A flexible capacitive coupler assembly includes a flexible dielectric substrate assembly having a front surface and a rear surface, the front surface having thereon a macroscopic metal capacitive pad. A package supports the flexible dielectric substrate. An electrical connection is made to package wiring or leads on the flexible dielectric substrate to establish electrical contact with a computer subsystem.Type: GrantFiled: March 27, 2006Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Matthew J. Farinelli, Robert B. Garner, Winfried W. Wilcke
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Patent number: 6393023Abstract: A system and method for acknowledging receipt of messages within a packet based communication network. A sending node generates a data packet within an upper layer, and transmits the data packet to a receiving node using a lower layer. The lower layer generates and transmits a pseudo reply packet to the upper layer in response to an acknowledgment received from the receiving node. The pseudo reply packet notifies the upper layer of the sending node that the receiving node successfully received the data packet and removes the burden of having an upper layer of the receiving node generate an actual reply packet.Type: GrantFiled: May 8, 1998Date of Patent: May 21, 2002Assignee: Fujitsu LimitedInventors: Takeshi Shimizu, Wolf-Dietrich Weber, Patrick J. Helland, Thomas M. Wicki, Winfried W. Wilcke