Abstract: A memory architecture which includes a plurality of memory cells arranged in rows and columns. A word line is connected to each row of memory cells, and a plurality of bit lines are connected to each column of memory cells. Providing that more than one bit line is connected to each column of memory cells improves the performance of large memories, provides reduced access times without having to increase the size of the memory, and provides that a large memory consumes less power. The bit lines may each be formed of the same material, or they may be formed of different material depending on the application. The memory cells may be disposed in a plurality of arrays, and the arrays may be symmetrical (i.e. where each array is the same size) or asymmetrical (i.e. where the arrays are not the same size).