Patents by Inventor Wing Han Leung
Wing Han Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7952938Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: GrantFiled: May 4, 2010Date of Patent: May 31, 2011Assignee: Spansion LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Publication number: 20100208527Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: ApplicationFiled: May 4, 2010Publication date: August 19, 2010Applicant: SPANSION LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Patent number: 7746705Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: GrantFiled: December 10, 2007Date of Patent: June 29, 2010Assignee: Spansion LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Publication number: 20090147589Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: Spansion LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Patent number: 7020021Abstract: A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.Type: GrantFiled: November 4, 2004Date of Patent: March 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Wing-Han Leung, Richard M. Fastow, Yue-Song He, Sheung-Hee Park
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Patent number: 6937518Abstract: A method of programming a memory device comprises applying a first programming voltage to one of a plurality of wordlines, corresponding to a cell to be programmed. The first programming voltage is substantially equal to the desired threshold voltage. A second programming voltage is also applied to one of a plurality of bitlines, corresponding to the cell to be programmed. The second programming voltage gradually increases from a low level toward a high level. The first programming voltage and second programming voltage are removed when the corresponding bitline current begins to decrease.Type: GrantFiled: July 10, 2003Date of Patent: August 30, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Sheung Hee Park, Wing Han Leung, Richard M. Fastow
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Patent number: 6819615Abstract: A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the Ids versus Vgate curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.Type: GrantFiled: October 31, 2002Date of Patent: November 16, 2004Assignee: Advanced Micro Device, Inc.Inventors: Richard M. Fastow, Wing Han Leung, John Wang
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Patent number: 6781885Abstract: In programming the threshold voltage of a memory cell transistor having a substrate, a gate insulator on the substrate, a floating gate on the gate insulator, an insulating layer on the floating gate, and a control gate on the insulating layer, and a source and drain in the substrate, a voltage difference is applied between the drain and source of the transistor and negative voltage is applied to the substrate of the transistor. An increasing voltage is applied to the control gate of the transistor, and, during application of that increasing voltage, a succession of verification tests are undertaken at a corresponding succession of times separated by chosen time intervals to verify if the transistor has been programmed to a chosen threshold voltage.Type: GrantFiled: March 5, 2003Date of Patent: August 24, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Sheung Hee Park, Richard Fastow, Wing Han Leung
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Patent number: 6275415Abstract: A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated.Type: GrantFiled: October 12, 1999Date of Patent: August 14, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Sameer S. Haddad, Ravi S. Sunkavalli, Wing Han Leung, John Chen, Ravi Prakash Gutala, Colin Bill, Vei-Han Chan