Abstract: A wireless charging receiver as described herein includes a configurable rectifier configured to convert an alternating current input to a direct current output in a single processing stage, wherein the configurable rectifier comprises one or more diodes, and a controller communicatively coupled to the one or more diodes and configured to select one of a plurality of mode cycling schemes and control a present operating mode of the active diodes according to a selected mode cycling scheme. Additionally, an active diode as described herein includes a comparator, a gate driver, a power transistor, and a delay compensation circuit for compensation of at least one of a turn-on delay and a turn-off delay of the active diode, the delay compensation circuit including analog feedback loops.

Abstract: A wireless charging receiver as described herein includes a configurable rectifier configured to convert an alternating current input to a direct current output in a single processing stage, wherein the configurable rectifier comprises one or more diodes, and a controller communicatively coupled to the one or more diodes and configured to select one of a plurality of mode cycling schemes and control a present operating mode of the active diodes according to a selected mode cycling scheme, Additionally, an active diode as described herein includes a comparator, a gate driver, a power transistor, and a delay compensation circuit for compensation of at least one of a turn-on delay and a turn-off delay of the active diode, the delay compensation circuit including analog feedback loops.

Abstract: Techniques are provided to tune a gate-drive control signal for a switching device. In an aspect, a device is provided that includes a dead-time generator circuit, a first dead-time tuner circuit and a second dead-time tuner circuit. The dead-time generator circuit generates a control signal for a first switching device that is coupled to a second switching device via a switching node. The first dead-time tuner circuit generates, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device. The second dead-time tuner circuit generates, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until a first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device.

Abstract: Techniques are provided to tune a gate-drive control signal for a switching device. In an aspect, a device is provided that includes a dead-time generator circuit, a first dead-time tuner circuit and a second dead-time tuner circuit. The dead-time generator circuit generates a control signal for a first switching device that is coupled to a second switching device via a switching node. The first dead-time tuner circuit generates, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device. The second dead-time tuner circuit generates, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until a first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device.

Abstract: A differential difference amplifier Type-III compensator of a voltage-mode switching converter can be designed to help regulate an input voltage from a power source. A voltage-mode switching converter can comprise a power stage and a voltage-mode controller. A voltage-mode controller can comprise a compensator, which comprises a differential difference amplifier. The design of the differential difference amplifier Type-III compensator can reduce production costs and enhance power transfer efficiencies.

Abstract: Hybrid buck converters that incorporate switching converter and auxiliary linear regulators are described. The auxiliary linear regulators are automatically activated during load transients to source or sink large currents to the output to achieve fast transient responses and are automatically deactivated during steady states to maintain high power efficiencies. With the proposed control scheme of automatic loop transition between linear and switching regulation loops, the power management interface design is simplified while the transient response performances are improved without compromising the power efficiencies.

Abstract: A differential difference amplifier Type-III compensator of a voltage-mode switching converter can be designed to help regulate an input voltage from a power source. A voltage-mode switching converter can comprise a power stage and a voltage-mode controller. A voltage-mode controller can comprise a compensator, which comprises a differential difference amplifier. The design of the differential difference amplifier Type-III compensator can reduce production costs and enhance power transfer efficiencies.

Abstract: Hybrid buck converters that incorporate switching converter and auxiliary linear regulators are described. The auxiliary linear regulators are automatically activated during load transients to source or sink large currents to the output to achieve fast transient responses and are automatically deactivated during steady states to maintain high power efficiencies. With the proposed control scheme of automatic loop transition between linear and switching regulation loops, the power management interface design is simplified while the transient response performances are improved without compromising the power efficiencies.

Abstract: An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged.

Abstract: A pixel element for an image sensor comprising, a photodiode and a reset transistor coupled to an input node, wherein said reset transistor is a PMOSFET coupled between said input node and the supply voltage, and wherein said pixel further comprises parallel complementary signal paths.

Abstract: An optical sensor has at least one pixel that generates an output voltage that changes at a rate dependent on the light intensity incident on the pixel. The time for the pixel output voltage to change from a first predefined level to a second predefined level is measured, so as to produce an output indicative of the incident light intensity.

Abstract: An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged.

Abstract: An exponential charge pump uses a number of identical or similar charging stages, each having a first and second capacitor. During a first clock phase, the first capacitor of each stage is charged by the second capacitor of the preceding stage, and, during a complementary second clock phase, the positive plate of the first capacitor of each stage is pushed to an increased voltage by the first capacitor of the preceding stage and charges the second capacitor of the next stage to the increased voltage at the same time. A similar mechanism occurs to the second capacitors in each stage, but with complementary timing. The increased voltage of the first capacitor of the last stage is pumped to an output capacitor during the second clock phase, and the increased voltage of the second capacitor of the last stage is pumped to an output capacitor during the first clock phase.

Abstract: An exponential charge pump uses a number of identical or similar charging stages, each having a first and second capacitor. During a first clock phase, the first capacitor of each stage is charged by the second capacitor of the preceding stage, and, during a complementary second clock phase, the positive plate of the first capacitor of each stage is pushed to an increased voltage by the first capacitor of the preceding stage and charges the second capacitor of the next stage to the increased voltage at the same time. A similar mechanism occurs to the second capacitors in each stage, but with complementary timing. The increased voltage of the first capacitor of the last stage is pumped to an output capacitor during the second clock phase, and the increased voltage of the second capacitor of the last stage is pumped to an output capacitor during the first clock phase.

Abstract: A method and apparatus are disclosed for single-inductor multiple-output switching converter design. With the proposed freewheel switching control, this converter operates in a pseudo-continuous conduction mode (PCCM) and is capable of handling large load currents with a much smaller current ripple and peak inductor current, while retaining low cross regulation. It can also work in discontinuous conduction mode (DCM) for high efficiency at light loads. This design can be applied to have single or multiple outputs and for different types of DC-DC conversions.

Abstract: An optical sensor has at least one pixel that generates an output voltage that changes at a rate dependent on the light intensity incident on the pixel. The time for the pixel output voltage to change from a first predefined level to a second predefined level is measured, so as to produce an output indicative of the incident light intensity.

Abstract: An exponential charge pump uses a number of identical or similar charging stages, each having a first and second capacitor. During a first clock phase, the first capacitor of each stage is charged by the second capacitor of the preceding stage, and, during a complementary second clock phase, the positive plate of the first capacitor of each stage is pushed to an increased voltage by the first capacitor of the preceding stage and charges the second capacitor of the next stage to the increased voltage at the same time. A similar mechanism occurs to the second capacitors in each stage, but with complementary timing. The increased voltage of the first capacitor of the last stage is pumped to an output capacitor during the second clock phase, and the increased voltage of the second capacitor of the last stage is pumped to an output capacitor during the first clock phase.

Abstract: A single inductor multiple-input multiple-output (SI-MIMO) switching converter time-multiplexes different input power sources through only one inductor to provide multiple regulated output voltages, which can be used to power up different blocks of a portable electronic device (or whatever else it is used for) and at the same time to charge up a rechargeable battery. Power multiplexing is achieved by input switches that are also the switching elements of the switching converter, thus eliminating an additional power multiplexer.

Abstract: A voltage mirror circuit using a symmetrically matched transistor structure is provided. The circuit includes an input reference voltage node on a first side of said circuit and an output mirror voltage node on a second side of said circuit, and a plurality of matched transistor pairs wherein the transistors in each pair have the same aspect ratio and wherein one transistor in each pair is provided on the first side of the circuit and the second transistor in each pair is provided on the second side of said circuit. The transistor pairs may include pairs of NMOS transistors and pairs of PMOS transistors or pairs of bipolar npn transistors and pairs of bipolar pnp transistors.

Abstract: A pixel element for an image sensor comprising, a photodiode and a reset transistor connected to an input node, wherein said reset transistor is a PMOSFET connected between said input node and the supply voltage, and wherein said pixel further comprises parallel complementary signal paths.