Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

Abstract: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode.

Abstract: A switching apparatus for switching packetized voice traffic between a plurality of communication devices, the switching apparatus comprises a multi-layer switch, a plurality of communication ports, control means and ingress processing means, said packetized voice traffic comprises call control packets and medium packets which are exchanged between the communication devices via said communication ports, wherein medium packet traffic from a first communication device to a second communication device is split into a first call segment and a second call segment, the first call segment originates from said first communication devices and terminates at said switching apparatus, the second call segment originates from said switching apparatus and terminates at said second communication device, each medium packet from said first communication device is processed by said ingress processing means of said switching apparatus before onward transmission to said second communication device.

Abstract: An admission scheme for a communication network comprising the step of:—a) acquiring and storing the MAC address of a device on admitting the device to the communication network, b) checking the source MAC address of a data packet before said data packet is admitted into the communication network, and c) admitting a data packet into the communication network only if the MAC address is registered with the communication network.

Abstract: A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

Abstract: A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have high signal to noise ratio, high signal margin, and tolerance to process variations, to form a single high performance static memory cell. This new cell has independent read and write paths, which allow for separate optimization of the read (R) and write (W) events, and enable dual-port R/W operation. Furthermore, storage node disturbance during the read and write operations are eliminated, which greatly improves cell stability and scalability for future technologies.

Abstract: A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode and changing a voltage of a source of the gated diode in an evaluation mode. One or more isolation devices may be connected between each small amplitude signal and a gate of the gated diode, wherein the isolation device passes the small amplitude signal to the gate of the gated diode in the sampling mode, and isolates the small amplitude signal from the gate in the evaluation mode for amplification and performing fast logic operations (logic functions). The disclosed gated diode logic circuits overcome the Vt variation problem in FETs by detecting and amplifying the small logic signals utilizing gated diodes that have relatively low Vt variation.

Abstract: A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

Abstract: An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

Abstract: A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value.

Abstract: A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line; (2) a two terminal semiconductor, the first terminal of the two terminal semiconductor device coupled to the second terminal of the write switch, and the second terminal of the two terminal semiconductor device coupled to an at least one second control line, wherein the two terminal semiconductor device has a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and has a lower capacitance when the voltage on the first terminal relative to the second terminal is less than the threshold voltage; (3) a read select switch, the control terminal of the read select switch coupled to an at least one second control line, the first terminal of the read select switch coupled to the at least one bitline; and (4) a read switch, the control terminal of the read switch couple

Abstract: A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Abstract: A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch.

Abstract: A DRAM is disclosed which includes a single ended bitline structure, a single ended global bitline structure, primary sense amplifiers with data storage and data write-back capability and with capability to decouple from the global bitlines, a full-wordline I/O structure where essentially all memory cell that belong to the same wordline are being operated on, and a pipelined architecture. The DRAM further includes a small voltage swing design. The primary sense amplifiers can include more than one amplification stages. Such a DRAM is suitable for applications in conjunction with processors as an embedded DRAM.

Abstract: An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

Abstract: A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.

Abstract: A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.