Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Abstract: In a data processing system, a device controller, configured to control data transfers between a processor unit and a peripheral device on an input/output bus, is provided with apparatus that permits a data transfer cycle to continue until all data has been transferred, or to allow for interruption of the data transfer cycle by another device controller requesting access to the input/output via a request signal. During a data transfer cycle the apparatus resonds to detection of the request signal to interrupt the data transfer cycle after a predetermined number of data words are transferred, permitting access to the input/output bus for other of the device controllers. In absence of the request signal, the apparatus permits the data transfer to continue until all data has been transferred between the peripheral device and the processor unit.

Abstract: Fault tolerant apparatus for generating error correcting code and, simultaneous therewith, checking the correctness of the generation, for blocks of data with which the error correcting code is associated and transmitted to a storage medium. The apparatus includes a pair of programmable control devices configured to selectively operate in one of two modes: A first mode in which data being transferred to the storage medium is monitored for generation of an error correcting code to be associated and stored with each data block, and a second mode in which the data being transferred is monitored for detecting errors that may be contained in the data. During data transmission to the storage device, one of the control devices operates in the first mode, while the other control device operates in the second mode to check operation of the first device.

Abstract: In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs).