Abstract: A phase lock loop (PLL) includes a phase detector configured to output a signal indicative of a phase difference between a reference signal and a feedback signal, a loop filter configured to filter an output of the phase detector, and a voltage-controlled oscillator (VCO) configured to output an oscillating signal having a frequency corresponding to an output of the loop filter. The PLL further includes a frequency divider configured to output the feedback signal by frequency dividing the oscillating signal output by the VCO, and a reset circuit configured to reset the frequency divider in an initialization mode such that a phase difference between the reference signal and the feedback signal corresponds to a lock angle of the PLL.

Abstract: A vector network analysis system and a method of measuring use offset stimulus signals to stimulate a balanced device under test (DUT) to determine performance parameters. The system includes an offset stimulus source that provides a plurality of stimulus signals and a vector network analyzer. At least one stimulus signal is offset from another stimulus signal of the plurality in one or both of frequency and time-varying phase. The offset stimulus source includes a first signal source and a second signal source that respectively provides the offset stimulus signals. The method of measuring includes generating the offset stimulus signals and applying the offset stimulus signals to a balanced port of the DUT to stimulate the DUT. The performance parameters are determined from measurements of the offset stimulus signals and one or more response signals from the stimulated DUT.

Abstract: An adaptive cycle-slipped detector (“ACSD”) for use in a Phase-Locked Loop (“PLL”) circuit. The ACSD may include a phase comparator, a phase shifter in signal communication with the phase comparator, and a cycle-slipped detector (“CSD”) in signal communication with the phase shifter.

Abstract: A dual spectrum analyzer measurement system reduces the effects of noise on acquired measurements, enabling power of a received input signal, and the noise of each spectrum analyzer in the dual spectrum analyzer measurement system, to be determined.

Abstract: A signal synthesizer includes a high frequency offset stage having a high frequency offset source and frequency translation element in the feedback path of a dual-oscillator offset loop synthesizer. The signal synthesizer achieves low phase noise via noise cancellation when used to provide the first local oscillator of a spectrum analyzer and when the second local oscillator of the spectrum analyzer provides the high frequency offset source to the signal synthesizer.