Abstract: Methods for manufacturing memory resistor devices and memory resistor devices manufactured according to such methods. A method includes depositing a first layer of dielectric material onto a substrate comprising a first electrode; bombarding the deposited first layer with an ion beam to create one or more defects in the first layer; depositing a second electrode such that the deposited first layer is between the first electrode and the second electrode; electroforming the first layer by applying an electroforming voltage between the first electrode and the second electrode.

Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Abstract: Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

Abstract: A method for manufacturing a memory resistor device. A first layer of a dielectric material is deposited onto a first electrode. A subsection of the first layer of the dielectric material is removed to expose one or more edges of the dielectric material and a second layer of the dielectric material is deposited to create one or more boundaries between the one or more edges of the first layer of the dielectric material and the second layer of the dielectric material. A second electrode is provided, wherein the one or more boundaries between the one or more edges of the first layer of the dielectric material and the second layer of the dielectric material extend at least partially from the first electrode to the second electrode.

Abstract: The invention of this straw is designed to turn the straw into one of reusable tableware, thereby reducing or even avoiding the use of disposable plastic straws, reducing their negative impact on the environment and health, and improving people's lives. Reducing the amount of disposable plastic straws is one of the most effective ways to reduce the damage of plastic waste to the nature. The straw in this invention has a pair of tabs affixed to the edge of the straw opening for easy opening of the straw.

Abstract: A system and method for management of updates across a plurality of enterprise computing devices. The system is configured to receive telemetry about the enterprise computing devices that will be used to develop a rollout strategy for upcoming updates. The system provides IT administrators with a user interface for modifying and customizing the rollout strategy. The proposed system and method can significantly improve the efficiency of regular update deployments to enterprise computing devices, and reduce the network cost associated with such deployments.

Abstract: A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textured boundary surface between the first electrode and the dielectric layer. The textured boundary surface promotes the formation of a conductive pathway in the dielectric layer between the first electrode and the second electrode.

Abstract: A system and method for management of updates across a plurality of enterprise computing devices. The system is configured to receive telemetry about the enterprise computing devices that will be used to develop a rollout strategy for upcoming updates. The system provides IT administrators with a user interface for modifying and customizing the rollout strategy. The proposed system and method can significantly improve the efficiency of regular update deployments to enterprise computing devices, and reduce the network cost associated with such deployments.

Abstract: A torsion bar restraint system for tracked combat vehicles that aids in the improvement of occupant survival rates when associated with asymmetric threats. The blast mitigating restraint system can reduce the dynamic deflection of torsion bars based on the severity of the blast impulse as needed. Systems comprise one or more components that secure the torsion bar to the hull for protecting against dynamic deflection and lateral displacement. The two disclosed components, an end restraint device and an M-Ring restraining device, can be used in conjunction or independently from each other based on the type of threat likely to be encountered.

Abstract: The invention of this straw is designed to turn the straw into one of reusable tableware, thereby reducing or even avoiding the use of disposable plastic straws, reducing their negative impact on the environment and health, and improving people's lives. Reducing the amount of disposable plastic straws is one of the most effective ways to reduce the damage of plastic waste to the nature. The straw in this invention has a pair of tabs affixed to the edge of the straw opening for easy opening of the straw.

Abstract: A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textured boundary surface between the first electrode and the dielectric layer. The textured boundary surface promotes the formation of a conductive pathway in the dielectric layer between the first electrode and the second electrode.

Abstract: A dicer is provided with a power output shaft in the container, and deceleration components and cutter disks on the output shaft. The cutter disks comprises a slicing cutter disk and a dicing cutter disk, a block in the container cover, a handle in the slicing cutter disk, and through-holes in the dicing cutter disk. The dicer is able to cut food into pieces with the same shape and size, and the dicing effectiveness is substantially perfect. The deceleration components have simple structure, which occupy small space and are convenient for household use. The handle is provided on the slicing cutter disk to facilitate detachment of the slice cutter disk for cleaning, and a through-hole is defined in the dicing cutter disk to facilitate detachment of the cutter disk for cleaning. The block makes the slicing cutter disk stable when rotating, to facilitate dicing.

Abstract: A torsion bar restraint system for tracked combat vehicles that aids in the improvement of occupant survival rates when associated with asymmetric threats. The blast mitigating restraint system can reduce the dynamic deflection of torsion bars based on the severity of the blast impulse as needed. Systems comprise one or more components that secure the torsion bar to the hull for protecting against dynamic deflection and lateral displacement. The two disclosed components, an end restraint device and an M-Ring restraining device, can be used in conjunction or independently from each other based on the type of threat likely to be encountered.

Abstract: A dicer includes a body providing a motor, a container and a container cover, a feeding tube extending on the container cover, a push rod in the feeding tube, a power output shaft in the container, deceleration components and cutter disks on the output shaft. The cutter disks comprises a slicing cutter disk and a dicing cutter disk, a block in the container cover, a handle in the slicing cutter disk, and through-holes in the dicing cutter disk. The dicer is able to cut food into pieces with the same shape and size. The deceleration components are provided in the container and have simple structure, which occupy small space. The handle is provided on the slicing cutter disk for facilitating to detach the slice cutter disk for cleaning, and a through-hole is defined in the dicing cutter disk for facilitating to detach the dicing cutter disk for cleaning.

Abstract: The invention generally relates to biological engineering of microorganisms and production of chemical compounds therefrom. More particularly, the invention relates to novel genetically engineered microorganisms for the fermentative production of p-aminobenzoic acid and related compounds from fermentable carbon substrates. The biologically derived PABA and related compounds from fermentable carbon substrates can be used in a number of applications including as a food supplement or raw materials for the syntheses of other industrial chemicals or polymers.

Abstract: A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. The age queue stores ID tags in respective age queue slots. Each ID tag in the age queue corresponds to a respective address of a load instruction in the request queue. In one embodiment, ID tags propagate through the age queue at a fixed rate of two at a time from a tail of the age queue to a head of the age queue. Arbitration control circuitry generates an enable bit vector that identifies the oldest ID tag in the age queue corresponding to the oldest load request in the request queue. The arbitration circuitry selects the identified oldest instruction in the request queue as the next to dispatch. In one embodiment, the core interface unit exhibits an input frequency that is a multiple of an internal operating frequency of the core interface unit.

Abstract: Functional oxygen-sensitive proteins are expressed in a heterologous diazotrophic cyanobacteria cell in the presence of ambient extracellular oxygen.

Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.

Abstract: A multiport connector which includes a housing having at least two aligned compartments, each compartment being structured and arranged to receive respective plugs. A multilayer printed wiring board separates the two compartments, the printed wiring board having circuit patterns on opposite sides of opposed non-conductive layers and a metal shielding layer intermediate the non-conductive layers. A first plurality of conductive contact fingers is disposed in one of the compartments, the first plurality of fingers having first portions for making electrical contact with one of the plugs and second portions for making contact with the circuit pattern on one of the non-conductive layers of the multilayer printed wiring board.

Abstract: An integrated circuit (IC) floorplan system includes an integration design system that executes IC floorplan software on a semiconductor die IC model. The IC floorplan software includes a timing tool database of the IC model. IC integrators utilize the IC floorplan software to evaluate logic block moves within the IC model. The IC floorplan software analyzes wire interconnect signal propagation time delays that result from prospective logic block moves with the IC model. The IC floorplan software reports back in real time whether or not a prospective move of a logic block from one location to another in the IC model will cause a timing failure due to a wire interconnect time delay exceeding a predetermined timing parameter.