Abstract: A wireless communication system and a precoder device for use in such system. The precoder device includes a delay element arranged to introduce a delay to a plurality of sub-channels of a signal at a transmitter end of the communication system; wherein the delay in a plurality of sub-channels are associated with a process time of a receiver component at a receiver end of the communication system.

Abstract: A wireless communication system and a precoder device for use in such system. The precoder device includes a delay element arranged to introduce a delay to a plurality of sub-channels of a signal at a transmitter end of the communication system; wherein the delay in a plurality of sub-channels are associated with a process time of a receiver component at a receiver end of the communication system.

Abstract: Systems, methods, and devices that employ a dynamic gate boost component (DGBC) to generate a desired boosted gate voltage to facilitate controlling an enhanced charge pump are presented. An enhanced charge pump can comprise a desired number of charge transfer switches (CTSs) and a desired number of DGBCs, wherein a DGBC can apply a desired boosted gate voltage to the gate of an associated CTS to control switching of the CTS. An auxiliary gate boost component (AGBC) of one circuit path can apply a desired boosted gate voltage to a CTS of another circuit path to control switching of that CTS. The AGBC and DGBC can operate to facilitate maintaining the overdrive voltages of all of the CTSs in the enhanced charge pump so that the overdrive voltages are essentially unchanged under various loading current conditions. Multiple enhanced charge pumps can be cascaded to produce a higher output voltage.

Abstract: Systems, methods, and devices that employ a dynamic gate boost component (DGBC) to generate a desired boosted gate voltage to facilitate controlling an enhanced charge pump are presented. An enhanced charge pump can comprise a desired number of charge transfer switches (CTSs) and a desired number of DGBCs, wherein a DGBC can apply a desired boosted gate voltage to the gate of an associated CTS to control switching of the CTS. An auxiliary gate boost component (AGBC) of one circuit path can apply a desired boosted gate voltage to a CTS of another circuit path to control switching of that CTS. The AGBC and DGBC can operate to facilitate maintaining the overdrive voltages of all of the CTSs in the enhanced charge pump so that the overdrive voltages are essentially unchanged under various loading current conditions. Multiple enhanced charge pumps can be cascaded to produce a higher output voltage.

Abstract: Described herein are switched capacitor charge pump designs for a 2n× voltage converter. The 2n× voltage converter is constructed by cascading n units of substantially identical unit cells, which are respectively composed of cross-coupled single cell doubler circuits. Dynamic inverters are used to completely activate and deactivate the power switches in the respective unit cells to increase area efficiency. The charge pump designs described herein are implemented with standard high-voltage CMOS processes without requiring MOSFET transistors with different threshold voltages, giving the charge pump a regular structure that simplifies design and layout and reduces production costs. In addition, techniques for constructing a charge pump according to the designs provided herein are described.

Abstract: Systems, methods, and devices that generate a desired boosted gate voltage to facilitate controlling a charge pump are presented. A multi-phase charge pump (e.g., two-phase CMOS charge pump) can comprise a desired number of switch cells (SCs), wherein each SC can include a gate boost switch control component, which employs two transistors (without the need for external circuitry), and generates a desired gate voltage, based at least in part on a desired clock signal, wherein the desired gate voltage is applied to a charge transfer switch, Mc, of the SC to facilitate transferring a voltage across the Mc to a node on the other side of the Mc, in each stage of the charge pump, wherein the SCs are associated with a desired number of flying capacitors to facilitate increasing the input voltage to a desired output voltage.

Abstract: Systems, methods, and devices that generate a desired boosted gate voltage to facilitate controlling a charge pump are presented. A multi-phase charge pump (e.g., two-phase CMOS charge pump) can comprise a desired number of switch cells (SCs), wherein each SC can include a gate boost switch control component, which employs two transistors (without the need for external circuitry), and generates a desired gate voltage, based at least in part on a desired clock signal, wherein the desired gate voltage is applied to a charge transfer switch, Mc, of the SC to facilitate transferring a voltage across the Mc to a node on the other side of the Mc, in each stage of the charge pump, wherein the SCs are associated with a desired number of flying capacitors to facilitate increasing the input voltage to a desired output voltage.

Abstract: Described herein are switched capacitor charge pump designs for a 2n× voltage converter. The 2n× voltage converter is constructed by cascading n units of substantially identical unit cells, which are respectively composed of cross-coupled single cell doubler circuits. Dynamic inverters are used to completely activate and deactivate the power switches in the respective unit cells to increase area efficiency. The charge pump designs described herein are implemented with standard high-voltage CMOS processes without requiring MOSFET transistors with different threshold voltages, giving the charge pump a regular structure that simplifies design and layout and reduces production costs. In addition, techniques for constructing a charge pump according to the designs provided herein are described.

Abstract: An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.

Abstract: An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.