Abstract: Techniques for data type conversion using an instruction are described. An exemplary instruction includes fields for an opcode, an identification of source operands, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert 32-bit floating point values from the identified source operands into 16-bit floating point values and store 16-bit floating point values in data element positions of the identified destination operand.

Abstract: Techniques for data type conversion are described. An example uses an instruction that is to include fields for an opcode, an identification of source operand location, and an identification of destination operand location, wherein the opcode is to indicate instruction processing circuitry is to convert a 16-bit floating-point value from the identified source operand location into a 32-bit floating point value and store that 32-bit floating point value in one or more data element positions of the identified destination operand.

Abstract: Techniques for data type conversion via instruction are described. An exemplary instruction is to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand.

Abstract: Systems, methods, and apparatuses relating to a scalable reservation station circuit implementing a single unified speculation state propagation and execution wakeup matrix in a processor are described.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a cross-lane packed data instruction on a partial (e.g., half) width processor with a minimal number of micro-operations are described. In one embodiment, a hardware processor core includes a decoder circuit to decode a single packed data instruction into only a first micro-operation and a second micro-operation, a packed data execution circuit to execute the first micro-operation and the second micro-operation, and a reservation station circuit coupled between the decoder circuit and the packed data execution circuit, the reservation station circuit comprising a first reservation station entry for the first micro-operation to store a first set of fields that indicate three or more input sources and a first destination, and a second reservation station entry for the second micro-operation to store a second set of fields to indicate three or more input sources and a second destination.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic two-pass execution of a partial flag updating instruction in a processor are described.

Abstract: A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.

Abstract: A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract: A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.

Abstract: A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered and the computations required to perform the division. The divisor is normalized by eliminating sign bits. The dividend is prescaled to eliminate one or more sign bits. Prescaling of the dividend may not be precise as sign bits of the dividend may be shifted out as groups of bits, rather than individual bits. Prescaling of the dividend may be adjusted to account for the fact that the divider considers multiple bits of the dividend at a time. Subsequent to prescaling and adjustment, the dividend may be adjusted in dependence upon the normalization of the divisor. Further adjustment may be utilized to maintain a significance relationship between the divisor and dividend. Subsequent to further adjustment, the division operation may be completed.

Abstract: An address generation unit (AGU) including a single adder and a recycling path. The recycling AGU may receive a plurality of operands at a first and at a second selection device to perform a first address generation operation. The adder may sum a portion of the operands to generate an output sum. Then, the output sum may be recycled back to the first selection device via the recycle path. The sum that is output from the adder may be recycled back to the first selection device one or more times via the recycle path depending on whether the first address generation operation requires one or more additional operands to be added to generate a corresponding address. Since the recycling AGU includes only a single adder, it may reduce the hardware necessary to perform the multiple computations that are typically required in an address generation operation without adversely affecting performance.