Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.

Abstract: An oscillator inverter circuit has an input at a first crystal node and drives a second crystal node of a crystal oscillator. The first node is lightly loaded by a gate of an input transistor that generates a buffered node. The buffered node voltage is converted to a varying current by a converter transistor. Another varying current through upper and lower amplifier transistors are mirrored to upper and lower current mirror transistors. The gate and drain of the lower current mirror transistor are connected to the gate of an output transistor that pulls down the second node with low impedance. The drain of the upper current mirror transistor diverts current from an output current source, changing pull-up current to the second node through a p-channel transistor. An input resistor between the first node and the buffered node provides a DC bias but blocks AC oscillation signals.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: A differential clock driver uses feedback to reduce timing skews between the true and complement differential outputs. Each of the differential outputs has a pull-up driver and a pull-down driver. Each pull-up or pull-down driver has an initial transistor and a final transistor in parallel to drive the output. A resistor separates gates of the initial and final transistors, causing a delay to enable the final transistor. A transmission gate provides feedback from the other output to the gate of the final transistor. When the other output is faster that the output being driven, the transmission gate transfers charge from the other output to the gate of the final transistor, causing it to speed up driving its output. This helps compensates for the timing skew between the outputs. Skews present on differential inputs can be compensated by the transmission gate feedback.