Patents by Inventor Winnie Victoria Wei-Ning Chen

Winnie Victoria Wei-Ning Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210234044
    Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.
    Type: Application
    Filed: July 28, 2020
    Publication date: July 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei Ning CHEN, Pang-Yen TSAI, Yasutoshi OKUNO
  • Publication number: 20210151434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Publication number: 20210050457
    Abstract: A method for forming a gate-all-around structure is provided. The method includes forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin. The first type of semiconductor layers includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer. The method also includes removing the second type of semiconductor layers. In addition, the method includes forming a gate to wrap around the first type of semiconductor layers.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsuan HSIAO, Wei-Sheng YUN, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE, Ling-Yen YEH
  • Patent number: 10886270
    Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer. The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10868009
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10825933
    Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsuan Hsiao, Wei-Sheng Yun, Winnie Victoria Wei-Ning Chen, Tung Ying Lee, Ling-Yen Yeh
  • Publication number: 20200321336
    Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Patent number: 10700066
    Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20200203342
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Publication number: 20200176567
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a first fin and a second fin formed over the substrate. The semiconductor structure further includes a first anti-punch through region formed in the first fin and a second anti-punch through region formed in the second fin and first nanostructures formed over the first fin and second nanostructures formed over the second fin. The semiconductor structure further includes a barrier layer formed over the second anti-punch through region and a first gate formed around the first nanostructures. The semiconductor structure further includes a second gate formed around the second nanostructures. In addition, an interface between the barrier layer and the second anti-punch through region is higher than an interface between the first anti-punch through region and the first gate.
    Type: Application
    Filed: January 3, 2020
    Publication date: June 4, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan HSIAO, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE
  • Publication number: 20200105518
    Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.
    Type: Application
    Filed: April 15, 2019
    Publication date: April 2, 2020
    Inventors: Winnie Victoria Wei-Ning CHEN, Andrew Joseph KELLY
  • Patent number: 10535738
    Abstract: Present disclosure provides a semiconductor structure including a first transistor and a second transistor. The first transistor includes a semiconductor substrate having a top surface and a first anti-punch through region doped with a first conductivity dopant at the top surface. The first transistor further includes a first channel over the top surface of the semiconductor substrate by a first distance. The second transistor includes a second anti-punch through region doped with a second conductivity dopant at the top surface of the semiconductor substrate. The second transistor further includes a second channel over the top surface of the semiconductor substrate by a second distance greater than the first distance. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsuan Hsiao, Winnie Victoria Wei-Ning Chen, Tung Ying Lee
  • Publication number: 20190378934
    Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Inventors: MENG-HSUAN HSIAO, WEI-SHENG YUN, WINNIE VICTORIA WEI-NING CHEN, TUNG YING LEE, LING-YEN YEH
  • Publication number: 20190164965
    Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 30, 2019
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Publication number: 20190131405
    Abstract: Present disclosure provides a semiconductor structure including a first transistor and a second transistor. The first transistor includes a semiconductor substrate having a top surface and a first anti-punch through region doped with a first conductivity dopant at the top surface. The first transistor further includes a first channel over the top surface of the semiconductor substrate by a first distance. The second transistor includes a second anti-punch through region doped with a second conductivity dopant at the top surface of the semiconductor substrate. The second transistor further includes a second channel over the top surface of the semiconductor substrate by a second distance greater than the first distance. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 2, 2019
    Inventors: MENG-HSUAN HSIAO, WINNIE VICTORIA WEI-NING CHEN, TUNG YING LEE
  • Publication number: 20110247691
    Abstract: Methods and devices of the invention perform an optical concentration by an expansion of usable spectral width of the incident energy. Preferred methods and devices of the invention concentrate optical energy by tuning it into a narrow spectral width to match the bandgap of another system component, such as an optical fiber, an optical sensor or a photovoltaic device that converts the optical energy. Embodiments of the invention include methods and devices for the spectral concentration of multi-wavelength light and subsequent transport of the concentrated output light.
    Type: Application
    Filed: October 23, 2009
    Publication date: October 13, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Paul Kit Lai Yu, Winnie Victoria Wei-Ning Chen