Abstract: A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

Abstract: In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. By eliminating the termination resistor at the end of the bus where the master devices are located the required drive current needed to produce a given output swing is reduced. The bus drivers and receivers are CMOS integrated circuits. The bus of the present invention is operable utilizing small swing signals which enable sufficient implementation of current mode drivers for low impedance bus signals. In particular, the bus input receiver of the present invention comprises a two stage buffered sampler/amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a single clock cycle using CMOS circuits.

Abstract: Four transistors, a pair of buffers, and an inverter are configured with the first transistor connected in a pull-up configuration, with the transistor drain connected to a first node and with the transistor gate connected to a second node. The second transistor is connected in a pull-down configuration, with the transistor gate connected to a (data) input line and with the transistor drain connected to the first node. The third transistor is also connected in the pull-up configuration, with the transistor gate connected to the first node and with the transistor drain connected to the second node. The fourth transistor is also connected in the pull-down configuration, with the transistor gate coupled by the inverter to the input line and with the transistor drain connected to the second node. The buffers are each connected between a respective one of the nodes and a respective one of two (data) output lines.

Abstract: A self-limiting scheme to prevent an over-erase condition of a one-transistor EEPROM cell. During an erase cycle, a drain voltage is fed back to a floating gate to counteract a positive erase voltage on the source of the memory cell and therein reduce the electric field across the tunnel oxide leading to the cessation of erase. In another scheme, the drain voltage is fed back to deactivate the erase voltage when a predetermined drain voltage value is exceeded.