Patents by Inventor Winston Shue
Winston Shue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060027460Abstract: A metal filled damascene structure with improved electromigration resistance and method for forming the same, the method including providing a semiconductor process wafer comprising damascene openings; and, depositing metal and at least one metal dopant according to an ECD process to from a metal filled damascene comprising a doped metal alloy portion.Type: ApplicationFiled: August 6, 2004Publication date: February 9, 2006Inventors: Chung Chang, Ming Tsai, Winston Shue
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Patent number: 6995089Abstract: A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.Type: GrantFiled: May 8, 2003Date of Patent: February 7, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Chou, Minghsing Tsai, Winston Shue
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Publication number: 20050263902Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.Type: ApplicationFiled: July 1, 2005Publication date: December 1, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Cheng-Lin Huang, Winston Shue, Mong-Song Liang
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Patent number: 6943111Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.Type: GrantFiled: February 10, 2003Date of Patent: September 13, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Cheng-Lin Huang, Winston Shue, Mong-Song Liang
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Publication number: 20040224509Abstract: A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.Type: ApplicationFiled: May 8, 2003Publication date: November 11, 2004Applicant: Taiwan Semicondutor Manufacturing Co.Inventors: Shih-Wei Chou, Minghsing Tsai, Winston Shue
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Patent number: 6793797Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.Type: GrantFiled: March 26, 2002Date of Patent: September 21, 2004Assignee: Taiwan SEmiconductor Manufacturing Co., LtdInventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang
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Publication number: 20040157431Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.Type: ApplicationFiled: February 10, 2003Publication date: August 12, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Jing-Cheng Lin, Cheng-Lin Huang, Winston Shue, Mong-Song Liang
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Patent number: 6706629Abstract: A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.Type: GrantFiled: January 7, 2003Date of Patent: March 16, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jing-Cheng Lin, Cheng-Lin Huang, Winston Shue, Mong-Song Liang
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Patent number: 6649513Abstract: A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.Type: GrantFiled: May 15, 2002Date of Patent: November 18, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ming-Hsing Tsai, Shih-Wei Chou, Winston Shue, Mong-Song Liang
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Publication number: 20030183530Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.Type: ApplicationFiled: March 26, 2002Publication date: October 2, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang
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Patent number: 6627527Abstract: A method of forming a low resistance metal silicide layer on a narrow width, conductive gate structure, has been developed. After formation of a metal silicide layer on a conductive gate structure via a self-aligned metal silicide (salicide), procedure, unreacted metal is removed via a selective wet etch procedure. Components of the wet etch procedure incorporated in the metal silicide layer, are next removed via a medium temperature—high vacuum anneal procedure. Removal of the wet etch components incorporated in the metal suicide layer allow a final anneal procedure to convert the metal silicide layer to a lower resistance metal silicide layer, without voids or agglomerated regions of metal silicide which may have formed during the final anneal if the incorporated wet etch components had not been removed.Type: GrantFiled: October 10, 2002Date of Patent: September 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Maureen Wang, Chi-Wei Chang, Winston Shue
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Patent number: 6555474Abstract: A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.Type: GrantFiled: January 29, 2002Date of Patent: April 29, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng Lin Huang, Minghsing Tsai, Winston Shue, Mong-Song Liang