Abstract: A computational engine may include an input configured to receive a first data packet and a second data packet, a context memory configured to store one or more contexts, and a set of computational elements coupled with the input and coupled with the context memory. The set of computational elements may be configured to generate a first output data packet by executing a first sequence of cryptographic operations on the first data packet, and generate a second output data packet by executing a second sequence of cryptographic operations on the second data packet and on a selected context of the one of the one or more contexts. The selected context may be associated with the second packet of data, and the context may be stored in the context memory prior to the execution of the first sequence of cryptographic operations.

Abstract: A computational engine may comprise a working memory configured to receive a first input message and a second input message, a context memory coupled with the working memory, wherein the context memory is configured to simultaneously store a first context corresponding to the first input message and a second context corresponding to the second input message, and a set of computational elements coupled with the working memory and coupled with the context memory, wherein the set of computational elements is configured to finish generating a first output digest based on the first input message and a first context after starting generation of a second output digest based the second input message and a second context and before finishing the generation of the second output digest.

Abstract: A random number generator may include an input configured to receive a plurality of entropy bits generated by an entropy source of a random number generator, wherein the random number generator is configured to generate a plurality of random numbers; and an entropy health monitor coupled with the input, wherein the entropy health monitor is configured to perform a corrective action based on the plurality of entropy bits.

Abstract: A computer system includes a security processor, a first scan chain coupled to the security processor, a non-secure element, and a second scan chain coupled to the non-secure element. The computer system also includes one or more test access port controllers to control operation of the first and second scan chains, and further includes debug control logic, coupled to the one or more test access port controllers, to enable the one or more test access port controllers to activate debug functionality on the second scan chain but not the first scan chain in response to a predefined condition being satisfied.

Abstract: A decompression engine may include an input configured to receive an input code comprises one or more bits from a bitstream of encoded data, a symbol decoder coupled with the input, where the symbol decoder is configured to calculate, based on the input code, a plurality of candidate addresses each corresponding to a code group. The symbol decoder may further include a group identifier module coupled with the symbol decoder, wherein the group identifier module is configured to identify one of the plurality of code groups corresponding to the input code, and a multiplexer coupled with the group identifier module, wherein the multiplexer is configured to select as a final address one of the plurality of candidate addresses corresponding to the identified code group.

Abstract: Embodiments of a workload management architecture may include an input configured to receive workload data for a plurality of commands, a DMA block configured to divide the workload data for each command of the plurality of commands into a plurality of job packets, a job packet manager configured to assign one of the plurality of job packets to one of a plurality of fixed function engines (FFEs) coupled with the job packet manager, where each of the plurality of FFEs is configured to receive one or more of the plurality of job packets and generate one or more output packets based on the workload data in the received one or more job packets.

Abstract: A system and method for securing a boot process on the electronic device using a hardware-based secure processor are provided. The hardware-based secure processor receives a boot instruction. In response to the received boot instruction, the hardware-based secure processor authenticates the boot code in hardware while stalling the processor. Once the boot code is authenticated, the processor is released from the stall and processes the boot code.

Abstract: A computational engine may include an input configured to receive a first data packet and a second data packet, a context memory configured to store one or more contexts, and a set of computational elements coupled with the input and coupled with the context memory. The set of computational elements may be configured to generate a first output data packet by executing a first sequence of cryptographic operations on the first data packet, and generate a second output data packet by executing a second sequence of cryptographic operations on the second data packet and on a selected context of the one of the one or more contexts. The selected context may be associated with the second packet of data, and the context may be stored in the context memory prior to the execution of the first sequence of cryptographic operations.

Abstract: A decompression engine may include an input configured to receive an input code comprises one or more bits from a bitstream of encoded data, a symbol decoder coupled with the input, where the symbol decoder is configured to calculate, based on the input code, a plurality of candidate addresses each corresponding to a code group. The symbol decoder may further include a group identifier module coupled with the symbol decoder, wherein the group identifier module is configured to identify one of the plurality of code groups corresponding to the input code, and a multiplexer coupled with the group identifier module, wherein the multiplexer is configured to select as a final address one of the plurality of candidate addresses corresponding to the identified code group.

Abstract: A key generator may comprise a first set of word registers each configured to store at least one word of a prior key, a set of computational elements coupled with the first set of word registers, one or more path selection elements coupled with the set of computational elements, wherein the one or more path selection elements are configured to select as a selected computational pathway a first computational pathway including a first subset of computational elements when a mode selection signal indicates a first mode, and select as the selected computational pathway a second computational pathway including a second subset of computational elements when the mode selection signal indicates a second mode, and a second set of word registers coupled with the set of computational elements, wherein each of the second set of word registers is configured to store at least one word of a new key generated by the selected computational pathway.

Abstract: A computational engine may comprise a working memory configured to receive a first input message and a second input message, a context memory coupled with the working memory, wherein the context memory is configured to simultaneously store a first context corresponding to the first input message and a second context corresponding to the second input message, and a set of computational elements coupled with the working memory and coupled with the context memory, wherein the set of computational elements is configured to finish generating a first output digest based on the first input message and a first context after starting generation of a second output digest based the second input message and a second context and before finishing the generation of the second output digest.

Abstract: A method of decoding Huffman-encoded data may comprise receiving a symbol associated with the Huffman encoded data, selecting a target group for the symbol based on a bit length value associated with the symbol, associating the symbol with the target group, associating the symbol with a code, and incrementing a starting code for each of a plurality of groups associated with a starting code that is equal to or greater than the starting code of the target group.

Abstract: A method of decoding Huffman-encoded data may comprise receiving a symbol associated with the Huffman encoded data, selecting a target group for the symbol based on a bit length value associated with the symbol, associating the symbol with the target group, associating the symbol with a code, and incrementing a starting code for each of a plurality of groups associated with a starting code that is equal to or greater than the starting code of the target group.

Abstract: Embodiments of a workload management architecture may include an input configured to receive workload data for a plurality of commands, a DMA block configured to divide the workload data for each command of the plurality of commands into a plurality of job packets, a job packet manager configured to assign one of the plurality of job packets to one of a plurality of fixed function engines (FFEs) coupled with the job packet manager, where each of the plurality of FFEs is configured to receive one or more of the plurality of job packets and generate one or more output packets based on the workload data in the received one or more job packets.

Abstract: A computer system includes a security processor, a first scan chain coupled to the security processor, a non-secure element, and a second scan chain coupled to the non-secure element. The computer system also includes one or more test access port controllers to control operation of the first and second scan chains, and further includes debug control logic, coupled to the one or more test access port controllers, to enable the one or more test access port controllers to activate debug functionality on the second scan chain but not the first scan chain in response to a predefined condition being satisfied.

Abstract: A random number generator may include an input configured to receive a plurality of entropy bits generated by an entropy source of a random number generator, wherein the random number generator is configured to generate a plurality of random numbers; and an entropy health monitor coupled with the input, wherein the entropy health monitor is configured to perform a corrective action based on the plurality of entropy bits.

Abstract: In an asynchronous transfer mode (ATM) endnode a method is provided by which ATM cells can experience a small delay from the ATM layer to the PHY layer to transmission on the ATM network.