Abstract: In certain embodiments, an apparatus comprises range matched filters and a Doppler-acceleration matched filter system. The matched filters are configured to receive radar return signals detected by an antenna and range match filter the radar return signals to place the radar return signals into range cells. The Doppler-acceleration matched filter system is configured to Doppler-acceleration process the radar return signals in the range cells to facilitate identification of one or more targets.

Abstract: In particular embodiments, analyzing data includes receiving sensor data generated in response to sensing one or more structures. The structural features of the sensor data are identified. Each structural feature is represented by one or more vectors. A score matrix that describes a plurality of distances among the vectors is generated. Vector pairs are formed from at least some of the vectors according to the distances of the score matrix. A layout of the structures is generated from the vector pairs.

Abstract: In certain embodiments, an apparatus comprises range matched filters and a Doppler-acceleration matched filter system. The matched filters are configured to receive radar return signals detected by an antenna and range match filter the radar return signals to place the radar return signals into range cells. The Doppler-acceleration matched filter system is configured to Doppler-acceleration process the radar return signals in the range cells to facilitate identification of one or more targets.

Abstract: In particular embodiments, analyzing data includes receiving sensor data generated in response to sensing one or more structures. The structural features of the sensor data are identified. Each structural feature is represented by one or more vectors. A score matrix that describes a plurality of distances among the vectors is generated. Vector pairs are formed from at least some of the vectors according to the distances of the score matrix. A layout of the structures is generated from the vector pairs.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The configurable signal processing logic may be configured to host one or more signal processing functions to allow data to be processed prior to its deposit into local memory.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. Configurable signal processing logic may be configured to host one or more signal processing functions which allow data to be autonomously accessed from the processor local memories, processed, and re-deposited in a local memory.

Abstract: A method for heterogeneous design and implementation of a complex electronic and software system having one or more static components and one or more programmable logic components in which a first programmable gate array area is provided with a first area having definable function blocks and routable interconnects, a first program for the first area is established and dedicated to a first logic design having a first set of functionality and interconnects, and a second programmable gate array area located within the first area is established, with the second area having definable function blocks and routable interconnects with resources and constraints formed by said first logic design. The logical and performance characteristics of the first area are established and frozen such that a high-level system tool may utilize and analyze a system design containing the first design in the gate sub-array as if it were a static design component.

Abstract: A quad-processor arrangement having 6 communications paths, one path between each of every possible pair of processors. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The communications paths are controlled and interfaced to the processors through field programmable logic, which allows the board to be configured both statically and dynamically to optimize the data transfer characteristics of the module to match the requirements of the application software. The programmable logic may be configured so that the module emulates other existing board architectures in order to support legacy applications.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. Configurable signal processing logic may be configured to host one or more signal processing functions which allow data to be autonomously accessed from the processor local memories, processed, and re-deposited in a local memory.

Abstract: A signal processing resource system with multiple sets of coefficients, channel context memories, and configuration control logic sets organized into signal processing personalities which are multiplexed in their use according to input data organization. Adaptable signal processing characteristics, processing suspension, processing resumption and seeding of signal processing context is provided. Control logic allows a data stream to be processed using multiple signal processing characteristics or “personalities” according to associations or groupings of coefficient, channel context, and control logic sets.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The configurable signal processing logic may be configured to host one or more signal processing functions to allow data to be processed prior to its deposit into local memory.

Abstract: An improved receiver for a non-coherent radar system including a mixer, an intermediate frequency amplifier, an envelope detector and a sliding window integrator. The receiver further includes a circuit connected to the sliding window integrator for providing enhanced signal-to-clutter ratios and azimuth resolution. The circuit comprises a pair of cascaded inverse filters wherein the first inverse filter compensates for the filter response of the sliding window integrator, and the second inverse filter compensates for the filter response of the radar system antenna due to its gain pattern.

Abstract: An improved receiver for a non-coherent radar system including a mixer, an intermediate frequency amplifier, an envelope detector and a sliding window integrator. The receiver further includes a circuit connected to the sliding window integrator for providing enhanced signal-to-clutter ratios and azimuth resolution. The circuit comprises a pair of cascaded inverse filters wherein the first inverse filter compensates for the filter response of the sliding window integrator, and the second inverse filter compensates for the filter response of the radar system antenna due to its gain pattern.

Abstract: A method and apparatus system for cancelling a leak-through signal component generated by an interfering transmitter from a received/leak-through signal comprising a multiplier for multiplying the received/leak-through signal by a reference signal provided from the interfering transmitter. The system further includes an integrator for integrating the output of the multiplier to generate an estimate of the gain and phase of the leak-through signal component. A gain and phase adjustor, responsive to the generated gain and phase estimates, is also included for adjusting the gain and phase of the reference signal to generate a cancellation signal that is a substantially gain and phase matched estimate of the leak-through signal. The generated cancellation signal is then subtracted from the received/leak-through signal to substantially cancel the leak-through signal component.

Abstract: Using an electronically scanned phased array antenna, a technique is developed for aligning a broad elevation beam along an isodop for use in synthetic aperture mapping. A beam steering controller algorithm for practical implementation of the technique is described. Implementation is realized by means of a beam steering controller and the radar computer. The controller first finds the space stabilized row and column for a given phase shifter. A look-up table furnished by the radar controller provides a slope correction as a function of row. The slope is multiplied by the element column to give the correct linear phase function. This term is then subtracted from the term used to point the beam peak.

Abstract: A programmable transform processor apparatus is disclosed which has an input and output for receiving and transmitting data and a data storage hardware for storing input data, as well as intermediate transform results. Arithmetic processing hardware processes input signals and has a multiplier accumulator having the multiplication function performed as a sequence of products combined in the accumulator portion of the multiplier accumulator simultaneous with the accumulator, accumulating the sum of the products therein. Data control hardware is operatively connected to the input/output means and to the data storage means and the arithmetic processing means for controlling the input and output of data for the input and output and the operation of the arithmetic processing hardware and the control of data to and from the data storage hardware.

Abstract: A pipeline processor of a radix-2 configuration including an input, intermediate and output processing sections for performing a discrete Fourier transformation (DFT) of an input array of N signal values to derive an output array of at least N signal values representative of the frequency transformation of the input array is disclosed. The input and output processing sections include first and second pluralities of cascadedly coupled computational elements respectively, which are governed to perform computations in a pipeline fashion and to propagate resulting interelement computed signal values through the input section in a first predetermined signal flow pattern and through the output section in a second predetermined signal flow pattern to render respectively a first intermediate array and the output array of signal values.

Abstract: A signal processor and method for processing N discrete samples of a quantized time domain signal to determine the frequency content or frequency spectrum of the time domain signal. Real and imaginary components of the quantized signal are processed in accordance with a decomposition technique that eliminates considerable hardware and reduces processing time. In a multiple stage processor, interstage multipliers are eliminated. One such disclosed processor includes a first data memory stage for storing the discrete samples of the quantized time domain signal and for retrieving the stored samples in a predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof. An L-point computational stage receives the retrieved samples of the quantized time domain signal and calculates real and imaginary output signals representing the solution to an L-point discrete Fourier transform.

Abstract: A spread beam computational section of a digital beam controller for an electronically controlled phased array radar includes a linear computational portion for computing a plurality of pairs of intermediate digital words corresponding to a desired spread beam radar pattern; and a non-linear computational portion for computing a spread beam phase command word from each computed pair of intermediate digital words which have been digitally rounded off. The instant disclosure is directed to apparatus which is disposed in the spread beam computational section for digitally rounding off each computed pair of intermediate digital words by adding randomly generated digital words to a residue bit portion thereof, preferably to the most significant bits of the residue bit portion.

Abstract: A digital processor comprising a network of arithmetic units and including apparatus for detecting and isolating a static bit fault therein is disclosed. A plurality of first arithmetic units of the network employ non-linear type operations. Each of the first arithmetic units arithmetically operate on a corresponding number of the binary coded digital input words of the network to produce a first output binary coded digital word which is coupled to the remaining network of arithmetic units. Corresponding to each of the first arithmetic units, there is provided a modulo 3 model to emulate in modulo 3 arithmetic the operation thereof and to compare the result of the modulo 3 emulation with the modulo 3 equivalent of a preselected word from the corresponding first arithmetic unit, the preselected word being intermediate the non-linear operation performed thereby. A non-equivalence condition resulting from the comparison is indicative of a static bit fault.