Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Abstract: A system for airflow management in an electronic enclosure includes a backplane assembly having at least one backplane connector, at least one daughter card, and components disposed on the daughter card oriented to facilitate front-to-back airflow, wherein inlet cooling air impinges on the backplane assembly and splits into at least two flow portions flowing in different directions along a surface defining the backplane assembly

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract: A counterbalancing arrangement for use with a compressive land grid array connector system provides a counterbalancing load element at a side of a system circuit board opposite a back side holding an integrated circuit chip substrate via the connector system. In a first aspect, the counterbalancing load element is a probe template and spacer element providing measurement across to the integrated circuiting. In another aspect, the counterbalancing load element is a mirror image integrated circuit land grid array connector system.

Abstract: A counterbalancing arrangement for use with a compressive land grid array connector system provides a counterbalancing load element at a side of a system circuit board opposite a back side holding an integrated circuit chip substrate via the connector system. In a first aspect, the counterbalancing load element is a probe template and spacer element providing measurement across to the integrated circuiting. In another aspect, the counterbalancing load element is a mirror image integrated circuit land grid array connector system.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Abstract: A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.

Abstract: Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle.