Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

Abstract: A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.

Abstract: Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.

Abstract: A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.

Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

Abstract: Localizing errors by: (i) running a testcase on a hardware processor and saving results; (ii) running the testcase on a software model of the processor and saving results; (iii) recording control flow information during the software run; (iv) determining a set of miscompare data storage locations by comparing the results from the hardware run with those from the software run; (v) based on the set of miscompare data storage locations and/or the control flow information, generating and running a modified version of the testcase that takes a different execution path when run on the software model than did the original testcase when run on the software model; and (vii) comparing the results from the hardware run and the results obtained from the modified software run to provide an indication of similarity between execution paths taken in these respective runs.

Abstract: Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.

Abstract: Localizing errors by: (i) running a testcase on a hardware processor and saving results; (ii) running the testcase on a software model of the processor and saving results; (iii) recording control flow information during the software run; (iv) determining a set of miscompare data storage locations by comparing the results from the hardware run with those from the software run; (v) based on the set of miscompare data storage locations and/or the control flow information, generating and running a modified version of the testcase that takes a different execution path when run on the software model than did the original testcase when run on the software model; and (vii) comparing the results from the hardware run and the results obtained from the modified software run to provide an indication of similarity between execution paths taken in these respective runs.

Abstract: A method includes executing a first post-silicon testing program by a reference model. During the execution of the first post-silicon testing program, one or more test-cases are generated. The first post-silicon testing program is executed in an offline generation mode. During execution of the first post-silicon testing program each test case is generated in a different memory location. After the execution, generating a second post-silicon testing program that is configured to execute the one or more test-cases. The method further includes executing the second post-silicon testing program on an acceleration platform.

Abstract: A method, apparatus and product for hardware verification using acceleration platform. The method comprising executing a first post-silicon testing program by a reference model, wherein during said executing the first post-silicon testing program one or more test-cases are generated; generating a second post-silicon testing program that is configured to execute the one or more test-cases; and executing the second post-silicon testing program on an acceleration platform.

Abstract: Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions.

Abstract: Test template may comprise a source code template instruction associated with source code commands. The source code template instruction is utilized in generation of a test. The generation of instructions associated with the source code template instruction takes into account utilization of shared resources by both the source code commands and by generated instructions that are generated by other template instructions.