Patents by Inventor Wiwat Tanwongwan
Wiwat Tanwongwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11637024Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.Type: GrantFiled: October 16, 2020Date of Patent: April 25, 2023Assignee: NXP B.V.Inventors: Wiwat Tanwongwan, Amornthep Saiyajitara, Nathapop Lappanitpullpol
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Patent number: 11114239Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.Type: GrantFiled: November 20, 2019Date of Patent: September 7, 2021Assignee: NXP B.V.Inventors: Chayathorn Saklang, Wiwat Tanwongwan, Amornthep Saiyajitara, Chanon Suwankasab
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Publication number: 20210151251Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.Type: ApplicationFiled: November 20, 2019Publication date: May 20, 2021Inventors: Chayathorn Saklang, Wiwat Tanwongwan, Amornthep Saiyajitara, Chanon Suwankasab
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Publication number: 20210035820Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Wiwat Tanwongwan, Amornthep Saiyajitara, Nathapop Lappanitpullpol
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Patent number: 10847385Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.Type: GrantFiled: October 9, 2018Date of Patent: November 24, 2020Assignee: NXP B.V.Inventors: Wiwat Tanwongwan, Amornthep Saiyajitara, Nathapop Lappanitpullpol
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Patent number: 10763203Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.Type: GrantFiled: February 8, 2019Date of Patent: September 1, 2020Assignee: NXP B.V.Inventors: Amornthep Saiyajitara, Wiwat Tanwongwan, Nathapop Lappanitpullpol
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Publication number: 20200258831Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Inventors: Amornthep Saiyajitara, Wiwat Tanwongwan, Nathapop Lappanitpullpol
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Publication number: 20200111685Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.Type: ApplicationFiled: October 9, 2018Publication date: April 9, 2020Inventors: Wiwat Tanwongwan, Amornthep Saiyajitara, Nathapop Lappanitpullpol
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Publication number: 20190229044Abstract: A lead frame is formed with exposed lead tips. The leads are not attached at their tips to any of a tie bar, a dam bar or an end bar, so when the lead frame is plated, the lead tips are plated. During packaging, after die attach and molding, when the lead frame is cut from the frame assembly, the lead tips are not cut, so the plating remains on the tips. This improves solder joint reliability when the package is mounted on a PCB. The lead frame has connection bars that run parallel to the leads from the tie bar to the end bar. The connection bars provide stability to the leads during wire bonding, but are cut from the lead frame after wire bonding.Type: ApplicationFiled: January 23, 2018Publication date: July 25, 2019Inventors: AMORNTHEP SAIYAJITARA, Wiwat Tanwongwan, Chanon Suwankasab, Ekapong Tangpattanasaeree
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Publication number: 20180226353Abstract: A lead frame used in semiconductor device assembly includes first and second opposing planar surfaces. A marking area is defined on the first planar surface. The marking area has a uniform background color that is different from a color of the first planar surface. A mark is formed in the marking area. The background color of the marking area contrasts with a color of the mark such that a clear image of the mark is easily captured with an image sensor. The mark preferably is a two-dimensional (2D) mark made of bumps and represents encoded information. The contrast between the background color and the mark is especially helpful when the lead frame has a roughened surface.Type: ApplicationFiled: February 7, 2017Publication date: August 9, 2018Inventors: Ekapong Tangpattanasaeree, Wiwat Tanwongwan, Amornthep Saiyajitara
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Patent number: 9824980Abstract: Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction.Type: GrantFiled: June 27, 2014Date of Patent: November 21, 2017Assignee: NXP B.V.Inventors: Chayathorn Saklang, Wiwat Tanwongwan
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Publication number: 20170133342Abstract: An integrated circuit package is provided. The integrated circuit package comprises: a die; a lead; and a bond wire comprising a first end coupled to the die and a second end coupled to the lead via bond. The bond wire further comprises: a first portion between a first bend in the bond wire and the bond and forming a first angle with respect to the lead; and a second portion forming a second angle with respect to the lead. The first bend is immediately between the first and second portions and is configured to reduce the angle of the bond wire with respect to the lead from the second angle to the first angle.Type: ApplicationFiled: October 31, 2016Publication date: May 11, 2017Inventors: Wiwat Tanwongwan, Piyarat Suwannakha, Chanon Suwankasab
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Publication number: 20170047275Abstract: Consistent with an example embodiment, there is a semiconductor device that comprises a lead frame assembly having a non-conductive material (NCM) sheet placed on a location of the lead frame assembly. A device die having a length, width, and thickness, is attached to the NCM sheet, the device die being attached to the NCM with an adhesive. The NCM sheet has a length and width greater than the length and width of the device die and the NCM sheet has a thickness less than the thickness of the device die. The NCM sheet mitigates wire bond lifting at device die bond pads by reducing bouncing of the wire bond leads owing to stress and movement of the lead frame assembly underneath the device die.Type: ApplicationFiled: August 11, 2015Publication date: February 16, 2017Inventor: Wiwat Tanwongwan
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Publication number: 20170033034Abstract: A packaged electronic device is disclosed, comprising: a package, a die and a first bondwire. The package comprises a leadframe. The leadframe comprises a first conducting leadframe element and a second conducting leadframe element that are separate from each other. The die comprises a first bondpad. The first bondwire electrically connects the first bondpad to the first conducting leadframe element. The die mechanically couples the first and second leadframe elements together.Type: ApplicationFiled: July 13, 2016Publication date: February 2, 2017Inventors: Chayathorn Saklang, Wiwat Tanwongwan
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Publication number: 20150380362Abstract: Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Chayathorn Saklang, Wiwat Tanwongwan