Patents by Inventor Wladimir Alejandro Plagges Martinez

Wladimir Alejandro Plagges Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-bit-mapping aware clock gating
    Patent number: 10157253
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: December 18, 2018
    Assignee: Synopsys, Inc.
    Inventors: Peter Wilhelm Josef Zepter, Wladimir Alejandro Plagges Martinez, Reiner Wilhelm Genevriere
  • MULTI-BIT-MAPPING AWARE CLOCK GATING
    Publication number: 20180107779
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.
    Type: Application
    Filed: October 17, 2016
    Publication date: April 19, 2018
    Applicant: Synopsys, Inc.
    Inventors: Peter Wilhelm Josef Zepter, Wladimir Alejandro Plagges Martinez, Reiner Wilhelm Genevriere