Abstract: An inexpensive digital phase detector with extended resolution for digital signal processing and for timing circuits for wireless, optical or wireline transmission systems.

Abstract: A DPD (digital phase error) circuit for measuring the phase skew between a first and a second clock signal for use in a variety of control systems and more particularly for use in DPLL (digital phase-locked loop) synchronizers. The DPD includes an ROG (ring oscillator generator) which has a string of inverter gates forming an RO (ring oscillator) and a ring counter. The ring counter operates to monitor the time elapsed from the occurrence of a reset clock signal edge by recording the number of oscillation periods of the RO. The RO and ring counter are coupled to an ROC (ring oscillator capture) unit which operates to capture the state of the RO and ring counter for every occurrence of a respective first clock signal edge and second clock signal edge so as to accurately evaluate the time elapsed since the occurrence of the preceding reset clock signal edge.

Abstract: An inexpensive and reliable DCDCI (digitally controlled duty cycle integration) circuit and method for efficiently converting a digital input signal into a high resolution analog control voltage for use in a variety of closed-loop control systems and more particularly for use in synchronizers. In particular, this invention enables a microsynchronizer to cost-effectively align a clock signal locally generated by a VCXO to multiple incoming clock signals operating at various frequencies for synchronization with a transmitter. The microsynchronizer designed in accordance with this invention integrates APLL and DPLL circuits into a compact and cost-effective design by consolidating analog and digital phase error processing in a PEG (phase error generator) design. The PEG converts the phase error information into differential signals which are subsequently presented to an AC-DC converter for producing high resolution analog control voltages for the VCXO.

Abstract: A universal synchronizer for use in a variety of telecommunications systems based on direct digital phase synthesis (DDPS) include digital and analog PLLs. The synchronizer may be used for wireless, optical, or wireline transmission systems and for a wide ranges of data rates. Digital phase detectors are used in the digital PLLs for comparing the phase of the local clock f.sub.L with the phase of a respective digital reference clock, and provides a respective phase error signal. A digital phase synthesis unit receives the phase error signal and a target phase error and produces a first and a second set of control signals for driving an error driver. The error driver generates the control voltage for adjusting the frequency of a VCXO that is used for all PLLs, to lock the respective PLL. The first set of control signal generates the control voltage for the digital PLLs, and the second set of control signals generates the control voltage for the analog PLLs and for the acquisition mode of operation of all PLLs.