Patents by Inventor Wlodzimerz S. Wiktor

Wlodzimerz S. Wiktor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods to control the droop when powering dual mode processors and associated circuits
    Patent number: 6919715
    Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 19, 2005
    Assignee: Intersil Corporation
    Inventors: Volodymyr A. Muratov, Michael Coletta, Wlodzimerz S. Wiktor
  • Methods to control the droop when powering dual mode processors and associated circuits
    Publication number: 20040090217
    Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.
    Type: Application
    Filed: September 23, 2003
    Publication date: May 13, 2004
    Applicant: INTERSIL CORPORATION
    Inventors: Volodymyr A. Muratov, Michael Coletta, Wlodzimerz S. Wiktor
  • Methods to control the droop when powering dual mode processors and associated circuits
    Patent number: 6680604
    Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: January 20, 2004
    Assignee: Intersil Corporation
    Inventors: Volodymyr A. Muratov, Michael Coletta, Wlodzimerz S. Wiktor
  • Methods to control the droop when powering dual mode processors and associated circuits
    Publication number: 20010045815
    Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.
    Type: Application
    Filed: February 22, 2001
    Publication date: November 29, 2001
    Inventors: Volodymyr A. Muratov, Michael Coletta, Wlodzimerz S. Wiktor