Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.

Abstract: A parallel data processor comprised of an array of identical cells concurrently performing identical operations under the direction of a central controller, and incorporating one or more of a special cell architecture including a segmented memory, conditional logic for preliminary processing, and circuitry for indicating when the cell is active, and programmable cell interconnection including cell bypass and alternate connection of edge cells.

Abstract: A plurality of identical processor cells arranged interconnected to form a data processor for processing digital data signals.Each of the cells includes an arithmetic processing element having three input terminals and two arithmetic output terminals. A plurality of memories connected to said arithmetic processing element are individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of said processing element in response to control signals from a controller. The memories are connected to the arithmetic processing element and the controller such that both logical and arithmetic operations are performed by the arithmetic element. The data processor includes n times m cells interconnected in an m by n matrix with interior cells and edge cells.

Abstract: A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit.

Abstract: A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit.

Abstract: A rectangular digital logic array for performing transformations on data matrices for solving wave equations, image processing problems and the like, includes a plurality of identical cells each having a processing element which receives one of its inputs from a single bit accumulator and provides its output to a similar single bit accumulator. The input accumulators of each row in the array are formed by a single parallel input, parallel output shift register and the output accumulators of each column in the array are similarly formed by a parallel input, parallel output shift register. The shift registers operate to connect each cell except those at the edge of the array with two neighboring cells along one axis and two neighboring cells along the orthogonal axis.