Patents by Inventor Woan-Yun HSIAO
Woan-Yun HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818887Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.Type: GrantFiled: March 4, 2022Date of Patent: November 14, 2023Assignee: EMEMORY TECHNOLOGY INC.Inventors: Hsueh-Wei Chen, Woan-Yun Hsiao, Wei-Ren Chen, Wein-Town Sun
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Publication number: 20230328978Abstract: A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.Type: ApplicationFiled: March 27, 2023Publication date: October 12, 2023Inventors: Wein-Town SUN, Woan-Yun HSIAO, Wei-Ren CHEN, Hsueh-Wei CHEN
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Patent number: 11751398Abstract: A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.Type: GrantFiled: August 12, 2021Date of Patent: September 5, 2023Assignee: eMemory Technology Inc.Inventors: Chia-Jung Hsu, Woan-Yun Hsiao, Wein-Town Sun
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Patent number: 11653503Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: August 28, 2020Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun Hsiao, Huang-Kui Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong-Jung Lin
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Publication number: 20230119398Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.Type: ApplicationFiled: March 4, 2022Publication date: April 20, 2023Inventors: Hsueh-Wei CHEN, Woan-Yun HSIAO, Wei-Ren CHEN, Wein-Town SUN
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Patent number: 11610103Abstract: A one time programmable non-volatile memory cell includes a storage element. The storage element includes a glass substrate, a buffer layer, a polysilicon layer and a metal layer. The buffer layer is disposed on the glass substrate. The polysilicon layer is disposed on the buffer layer. A P-type doped region and an N-type doped region are formed in the polysilicon layer. The metal layer is contacted with the N-type doped region and the P-type doped region. The metal layer, the N-type doped region and the P-type doped region are collaboratively formed as a diode. When a program action is performed, the first diode is reverse-biased, and the diode is switched from a first storage state to a second storage state. When a read action is performed, the diode is reverse-biased and the diode generates a read current.Type: GrantFiled: January 19, 2021Date of Patent: March 21, 2023Assignee: EMEMORY TECHNOLOGY INC.Inventors: Wein-Town Sun, Woan-Yun Hsiao
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Publication number: 20220085039Abstract: A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.Type: ApplicationFiled: August 12, 2021Publication date: March 17, 2022Applicant: eMemory Technology Inc.Inventors: Chia-Jung Hsu, Woan-Yun Hsiao, Wein-Town Sun
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Publication number: 20210249426Abstract: A one time programmable non-volatile memory cell includes a storage element. The storage element includes a glass substrate, a buffer layer, a polysilicon layer and a metal layer. The buffer layer is disposed on the glass substrate. The polysilicon layer is disposed on the buffer layer. A P-type doped region and an N-type doped region are formed in the polysilicon layer. The metal layer is contacted with the N-type doped region and the P-type doped region. The metal layer, the N-type doped region and the P-type doped region are collaboratively formed as a diode. When a program action is performed, the first diode is reverse-biased, and the diode is switched from a first storage state to a second storage state. When a read action is performed, the diode is reverse-biased and the diode generates a read current.Type: ApplicationFiled: January 19, 2021Publication date: August 12, 2021Inventors: Wein-Town SUN, Woan-Yun HSIAO
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Publication number: 20200395411Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
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Patent number: 10763305Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: September 18, 2018Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun Hsiao, Huang-Kui Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong-Jung Lin
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Publication number: 20190035850Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: September 18, 2018Publication date: January 31, 2019Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
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Patent number: 10090360Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: October 16, 2015Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Woan-Yun Hsiao, Ya-Chin King, Chrong-Jung Lin, Huang-Kui Chen, Tzong-Sheng Chang
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Publication number: 20160240775Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: October 16, 2015Publication date: August 18, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun HSIAO, Ya-Chin KING, Chrong-Jung LIN, Huang-Kui CHEN, Tzong-Sheng CHANG