Abstract: An integrated circuit for configuring memory block portions is provided. The integrated circuit may include a memory block that is partitioned into first and second memory block portions. The first memory block portion has a first memory type and the second memory block portion has a second memory type that is different than the first memory type. The integrated circuit further includes a control circuit configured to receive configuration data. The configuration data may include memory partition information for repartitioning the first and second memory block portions into first and second repartitioned memory block portions when a portion of the first memory block portion is unused. The memory partition information may also include a memory partitioning constraint, which includes a start point address for the second repartitioned memory block portion and a number of at least one memory segments to be partitioned in the second repartitioned memory block portion.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: An integrated circuit for configuring memory block portions is provided. The integrated circuit may include a memory block that is partitioned into first and second memory block portions. The first memory block portion has a first memory type and the second memory block portion has a second memory type that is different than the first memory type. The integrated circuit further includes a control circuit configured to receive configuration data. The configuration data may include memory partition information for repartitioning the first and second memory block portions into first and second repartitioned memory block portions when a portion of the first memory block portion is unused. The memory partition information may also include a memory partitioning constraint, which includes a start point address for the second repartitioned memory block portion and a number of at least one memory segments to be partitioned in the second repartitioned memory block portion.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.